From b8145e3881872fffbac15693c94536446f060330 Mon Sep 17 00:00:00 2001 From: Jack Carter Date: Mon, 15 Apr 2013 22:21:55 +0000 Subject: Mips assembler: Explicit floating point condition register recognition. This patch allows the assembler to recognize $fcc0 as a valid register for conditional move instructions. Corresponding test cases have been added. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179567 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/MC/Mips/mips-fpu-instructions.s | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'test/MC/Mips') diff --git a/test/MC/Mips/mips-fpu-instructions.s b/test/MC/Mips/mips-fpu-instructions.s index 29dc471db1..e515872f26 100644 --- a/test/MC/Mips/mips-fpu-instructions.s +++ b/test/MC/Mips/mips-fpu-instructions.s @@ -156,6 +156,8 @@ # CHECK: mtc0 $9, $8, 3 # encoding: [0x03,0x40,0x89,0x40] # CHECK: mfc2 $5, $7, 4 # encoding: [0x04,0x38,0x05,0x48] # CHECK: mtc2 $9, $4, 5 # encoding: [0x05,0x20,0x89,0x48] +# CHECK: movf $2, $1, $fcc0 # encoding: [0x01,0x10,0x20,0x00] +# CHECK: movt $2, $1, $fcc0 # encoding: [0x01,0x10,0x21,0x00] cfc1 $a2,$0 mfc1 $a2,$f7 @@ -175,3 +177,5 @@ mtc0 $9, $8, 3 mfc2 $5, $7, 4 mtc2 $9, $4, 5 + movf $2, $1, $fcc0 + movt $2, $1, $fcc0 -- cgit v1.2.3