From 1f1bd9a54d25d4e2c5da13c2cae7fa5e3d8acc9f Mon Sep 17 00:00:00 2001 From: Ben Langmuir Date: Thu, 12 Sep 2013 15:51:31 +0000 Subject: Partial support for Intel SHA Extensions (sha1rnds4) Add basic assembly/disassembly support for the first Intel SHA instruction 'sha1rnds4'. Also includes feature flag, and test cases. Support for the remaining instructions will follow in a separate patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190611 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/MC/X86/x86_64-encoding.s | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'test/MC/X86') diff --git a/test/MC/X86/x86_64-encoding.s b/test/MC/X86/x86_64-encoding.s index cfdf87f3e3..54d8637529 100644 --- a/test/MC/X86/x86_64-encoding.s +++ b/test/MC/X86/x86_64-encoding.s @@ -120,6 +120,14 @@ movd %mm1, %edx // CHECK: fixup A - offset: 5, value: CPI1_0-4 pshufb CPI1_0(%rip), %xmm1 +// CHECK: sha1rnds4 $1, %xmm1, %xmm2 +// CHECK: encoding: [0x0f,0x3a,0xcc,0xd1,0x01] +sha1rnds4 $1, %xmm1, %xmm2 + +// CHECK: sha1rnds4 $1, (%rax), %xmm2 +// CHECK: encoding: [0x0f,0x3a,0xcc,0x10,0x01] +sha1rnds4 $1, (%rax), %xmm2 + // CHECK: movq 57005(,%riz), %rbx // CHECK: encoding: [0x48,0x8b,0x1c,0x25,0xad,0xde,0x00,0x00] movq 57005(,%riz), %rbx -- cgit v1.2.3