From 407883b69b3bc10ebf053f5922d877b2e786d124 Mon Sep 17 00:00:00 2001
From: Akira Hatanaka <ahatanaka@mips.com>
Date: Fri, 26 Jul 2013 20:51:20 +0000
Subject: [mips] Fix FP conditional move instructions to have explicit FP
 condition code register operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187242 91177308-0d34-0410-b5e6-96231b3b80d8
---
 test/MC/Disassembler/Mips/mips32.txt    | 18 ++++++++++++++++++
 test/MC/Disassembler/Mips/mips32_le.txt | 18 ++++++++++++++++++
 2 files changed, 36 insertions(+)

(limited to 'test/MC')

diff --git a/test/MC/Disassembler/Mips/mips32.txt b/test/MC/Disassembler/Mips/mips32.txt
index d62488945c..6d02925ff7 100644
--- a/test/MC/Disassembler/Mips/mips32.txt
+++ b/test/MC/Disassembler/Mips/mips32.txt
@@ -266,6 +266,24 @@
 # CHECK: mov.s $f6, $f7
 0x46 0x00 0x39 0x86
 
+# CHECK: movf $3, $2, $fcc7
+0x00,0x5c,0x18,0x01
+
+# CHECK: movf.d $f4, $f2, $fcc7
+0x46,0x3c,0x11,0x11
+
+# CHECK: movf.s $f4, $f2, $fcc7
+0x46,0x1c,0x11,0x11
+
+# CHECK: movt $3, $2, $fcc7
+0x00,0x5d,0x18,0x01
+
+# CHECK: movt.d $f4, $f2, $fcc7
+0x46,0x3d,0x11,0x11
+
+# CHECK: movt.s $f4, $f2, $fcc7
+0x46,0x1d,0x11,0x11
+
 # CHECK: msub   $6,  $7
 0x70 0xc7 0x00 0x04
 
diff --git a/test/MC/Disassembler/Mips/mips32_le.txt b/test/MC/Disassembler/Mips/mips32_le.txt
index 52cf6eb1be..61e6fc868d 100644
--- a/test/MC/Disassembler/Mips/mips32_le.txt
+++ b/test/MC/Disassembler/Mips/mips32_le.txt
@@ -272,6 +272,24 @@
 # CHECK: move $3, $2
 0x25,0x18,0x40,0x00
 
+# CHECK: movf $3, $2, $fcc7
+0x01,0x18,0x5c,0x00
+
+# CHECK: movf.d $f4, $f2, $fcc7
+0x11,0x11,0x3c,0x46
+
+# CHECK: movf.s $f4, $f2, $fcc7
+0x11,0x11,0x1c,0x46
+
+# CHECK: movt $3, $2, $fcc7
+0x01,0x18,0x5d,0x00
+
+# CHECK: movt.d $f4, $f2, $fcc7
+0x11,0x11,0x3d,0x46
+
+# CHECK: movt.s $f4, $f2, $fcc7
+0x11,0x11,0x1d,0x46
+
 # CHECK: msub   $6,  $7
 0x04 0x00 0xc7 0x70
 
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