From e93c701cac2ac62bcd390b978604da76be9967d0 Mon Sep 17 00:00:00 2001 From: Tim Northover Date: Fri, 31 May 2013 13:47:25 +0000 Subject: ARM: fix VEXT encoding corner case The disassembly of VEXT instructions was too lax in the bits checked. This fixes the case where the instruction affects Q-registers but a misaligned lane was specified (should be UNDEFINED). Patch by Amaury de la Vieuville git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183003 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/MC/Disassembler/ARM/invalid-VEXTd-arm.txt | 5 +++++ 1 file changed, 5 insertions(+) create mode 100644 test/MC/Disassembler/ARM/invalid-VEXTd-arm.txt (limited to 'test/MC') diff --git a/test/MC/Disassembler/ARM/invalid-VEXTd-arm.txt b/test/MC/Disassembler/ARM/invalid-VEXTd-arm.txt new file mode 100644 index 0000000000..b76485e4a5 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-VEXTd-arm.txt @@ -0,0 +1,5 @@ +# RUN: llvm-mc --disassemble %s -triple=armv7 2>&1 | grep "invalid instruction encoding" + +# invalid imm4 value (0b1xxx) +# A8.8.316: if Q == '0' && imm4<3> == '1' then UNDEFINED; +0x8f 0xf9 0xf7 0xf2 -- cgit v1.2.3