From 81cd7ffe45730d5afd383ee8850e3ff1f48a1920 Mon Sep 17 00:00:00 2001
From: Bruno Cardoso Lopes <bruno.cardoso@gmail.com>
Date: Wed, 23 Jun 2010 19:50:39 +0000
Subject: Fix a tblgen bug.

Given the pattern below as an example:
list<dag> Pattern = [(set RC:$dst, (v4f32 (shufp:src3 RC:$src1,
                            (mem_frag addr:$src2))))];

The right reference resolving should lead to:
list<dag> Pattern = [(set VR128:$dst, (v4f32 (shufp:src3 VR128:$src1,
                            (mem_frag addr:$src2))))];
But was yielding:
list<dag> Pattern = [(set VR128:$dst, (v4f32 (shufp VR128:$src1,
                            (mem_frag addr:$src2))))];

Fix this by passing the right name when creating a new DagInit node.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106670 91177308-0d34-0410-b5e6-96231b3b80d8
---
 test/TableGen/usevalname.td | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)
 create mode 100644 test/TableGen/usevalname.td

(limited to 'test/TableGen')

diff --git a/test/TableGen/usevalname.td b/test/TableGen/usevalname.td
new file mode 100644
index 0000000000..1b31c8f150
--- /dev/null
+++ b/test/TableGen/usevalname.td
@@ -0,0 +1,24 @@
+// RUN: tblgen %s | FileCheck %s
+// XFAIL: vg_leak
+
+class Instr<list<dag> pat> {
+  list<dag> Pattern = pat;
+}
+
+class Reg {
+  int a = 3;
+}
+
+def VR128 : Reg;
+def mem_frag;
+def set;
+def addr;
+def shufp : Reg;
+
+multiclass shuffle<Reg RC> {
+  def rri : Instr<[(set RC:$dst, (shufp:$src3
+                                       RC:$src1, RC:$src2))]>;
+}
+
+// CHECK: shufp:src3
+defm ADD : shuffle<VR128>;
-- 
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