From 02fbffd4e8e1a28539b302e4de84203814898153 Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Wed, 30 Oct 2013 15:45:42 +0000 Subject: [mips][msa] Correct definition of bins[lr] and CHECK-DAG-ize related tests git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193695 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/Mips/msa/3r-b.ll | 194 ++++++++++++++++++++++++++---------------- 1 file changed, 121 insertions(+), 73 deletions(-) (limited to 'test') diff --git a/test/CodeGen/Mips/msa/3r-b.ll b/test/CodeGen/Mips/msa/3r-b.ll index 4f7955c673..5677d19eb7 100644 --- a/test/CodeGen/Mips/msa/3r-b.ll +++ b/test/CodeGen/Mips/msa/3r-b.ll @@ -90,183 +90,231 @@ declare <2 x i64> @llvm.mips.bclr.d(<2 x i64>, <2 x i64>) nounwind ; CHECK: bclr.d ; CHECK: st.d ; CHECK: .size llvm_mips_bclr_d_test -; + @llvm_mips_binsl_b_ARG1 = global <16 x i8> , align 16 -@llvm_mips_binsl_b_ARG2 = global <16 x i8> , align 16 +@llvm_mips_binsl_b_ARG2 = global <16 x i8> , align 16 +@llvm_mips_binsl_b_ARG3 = global <16 x i8> , align 16 @llvm_mips_binsl_b_RES = global <16 x i8> , align 16 define void @llvm_mips_binsl_b_test() nounwind { entry: %0 = load <16 x i8>* @llvm_mips_binsl_b_ARG1 %1 = load <16 x i8>* @llvm_mips_binsl_b_ARG2 - %2 = tail call <16 x i8> @llvm.mips.binsl.b(<16 x i8> %0, <16 x i8> %1) - store <16 x i8> %2, <16 x i8>* @llvm_mips_binsl_b_RES + %2 = load <16 x i8>* @llvm_mips_binsl_b_ARG3 + %3 = tail call <16 x i8> @llvm.mips.binsl.b(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2) + store <16 x i8> %3, <16 x i8>* @llvm_mips_binsl_b_RES ret void } -declare <16 x i8> @llvm.mips.binsl.b(<16 x i8>, <16 x i8>) nounwind +declare <16 x i8> @llvm.mips.binsl.b(<16 x i8>, <16 x i8>, <16 x i8>) nounwind ; CHECK: llvm_mips_binsl_b_test: -; CHECK: ld.b -; CHECK: ld.b -; CHECK: binsl.b -; CHECK: st.b +; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsl_b_ARG1)( +; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsl_b_ARG2)( +; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_binsl_b_ARG3)( +; CHECK-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R1]]) +; CHECK-DAG: ld.b [[R5:\$w[0-9]+]], 0([[R2]]) +; CHECK-DAG: ld.b [[R6:\$w[0-9]+]], 0([[R3]]) +; CHECK-DAG: binsl.b [[R4]], [[R5]], [[R6]] +; CHECK-DAG: st.b [[R4]], 0( ; CHECK: .size llvm_mips_binsl_b_test -; + @llvm_mips_binsl_h_ARG1 = global <8 x i16> , align 16 -@llvm_mips_binsl_h_ARG2 = global <8 x i16> , align 16 +@llvm_mips_binsl_h_ARG2 = global <8 x i16> , align 16 +@llvm_mips_binsl_h_ARG3 = global <8 x i16> , align 16 @llvm_mips_binsl_h_RES = global <8 x i16> , align 16 define void @llvm_mips_binsl_h_test() nounwind { entry: %0 = load <8 x i16>* @llvm_mips_binsl_h_ARG1 %1 = load <8 x i16>* @llvm_mips_binsl_h_ARG2 - %2 = tail call <8 x i16> @llvm.mips.binsl.h(<8 x i16> %0, <8 x i16> %1) - store <8 x i16> %2, <8 x i16>* @llvm_mips_binsl_h_RES + %2 = load <8 x i16>* @llvm_mips_binsl_h_ARG3 + %3 = tail call <8 x i16> @llvm.mips.binsl.h(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2) + store <8 x i16> %3, <8 x i16>* @llvm_mips_binsl_h_RES ret void } -declare <8 x i16> @llvm.mips.binsl.h(<8 x i16>, <8 x i16>) nounwind +declare <8 x i16> @llvm.mips.binsl.h(<8 x i16>, <8 x i16>, <8 x i16>) nounwind ; CHECK: llvm_mips_binsl_h_test: -; CHECK: ld.h -; CHECK: ld.h -; CHECK: binsl.h -; CHECK: st.h +; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsl_h_ARG1)( +; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsl_h_ARG2)( +; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_binsl_h_ARG3)( +; CHECK-DAG: ld.h [[R4:\$w[0-9]+]], 0([[R1]]) +; CHECK-DAG: ld.h [[R5:\$w[0-9]+]], 0([[R2]]) +; CHECK-DAG: ld.h [[R6:\$w[0-9]+]], 0([[R3]]) +; CHECK-DAG: binsl.h [[R4]], [[R5]], [[R6]] +; CHECK-DAG: st.h [[R4]], 0( ; CHECK: .size llvm_mips_binsl_h_test -; + @llvm_mips_binsl_w_ARG1 = global <4 x i32> , align 16 -@llvm_mips_binsl_w_ARG2 = global <4 x i32> , align 16 +@llvm_mips_binsl_w_ARG2 = global <4 x i32> , align 16 +@llvm_mips_binsl_w_ARG3 = global <4 x i32> , align 16 @llvm_mips_binsl_w_RES = global <4 x i32> , align 16 define void @llvm_mips_binsl_w_test() nounwind { entry: %0 = load <4 x i32>* @llvm_mips_binsl_w_ARG1 %1 = load <4 x i32>* @llvm_mips_binsl_w_ARG2 - %2 = tail call <4 x i32> @llvm.mips.binsl.w(<4 x i32> %0, <4 x i32> %1) - store <4 x i32> %2, <4 x i32>* @llvm_mips_binsl_w_RES + %2 = load <4 x i32>* @llvm_mips_binsl_w_ARG3 + %3 = tail call <4 x i32> @llvm.mips.binsl.w(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2) + store <4 x i32> %3, <4 x i32>* @llvm_mips_binsl_w_RES ret void } -declare <4 x i32> @llvm.mips.binsl.w(<4 x i32>, <4 x i32>) nounwind +declare <4 x i32> @llvm.mips.binsl.w(<4 x i32>, <4 x i32>, <4 x i32>) nounwind ; CHECK: llvm_mips_binsl_w_test: -; CHECK: ld.w -; CHECK: ld.w -; CHECK: binsl.w -; CHECK: st.w +; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsl_w_ARG1)( +; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsl_w_ARG2)( +; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_binsl_w_ARG3)( +; CHECK-DAG: ld.w [[R4:\$w[0-9]+]], 0([[R1]]) +; CHECK-DAG: ld.w [[R5:\$w[0-9]+]], 0([[R2]]) +; CHECK-DAG: ld.w [[R6:\$w[0-9]+]], 0([[R3]]) +; CHECK-DAG: binsl.w [[R4]], [[R5]], [[R6]] +; CHECK-DAG: st.w [[R4]], 0( ; CHECK: .size llvm_mips_binsl_w_test -; + @llvm_mips_binsl_d_ARG1 = global <2 x i64> , align 16 -@llvm_mips_binsl_d_ARG2 = global <2 x i64> , align 16 +@llvm_mips_binsl_d_ARG2 = global <2 x i64> , align 16 +@llvm_mips_binsl_d_ARG3 = global <2 x i64> , align 16 @llvm_mips_binsl_d_RES = global <2 x i64> , align 16 define void @llvm_mips_binsl_d_test() nounwind { entry: %0 = load <2 x i64>* @llvm_mips_binsl_d_ARG1 %1 = load <2 x i64>* @llvm_mips_binsl_d_ARG2 - %2 = tail call <2 x i64> @llvm.mips.binsl.d(<2 x i64> %0, <2 x i64> %1) - store <2 x i64> %2, <2 x i64>* @llvm_mips_binsl_d_RES + %2 = load <2 x i64>* @llvm_mips_binsl_d_ARG3 + %3 = tail call <2 x i64> @llvm.mips.binsl.d(<2 x i64> %0, <2 x i64> %1, <2 x i64> %2) + store <2 x i64> %3, <2 x i64>* @llvm_mips_binsl_d_RES ret void } -declare <2 x i64> @llvm.mips.binsl.d(<2 x i64>, <2 x i64>) nounwind +declare <2 x i64> @llvm.mips.binsl.d(<2 x i64>, <2 x i64>, <2 x i64>) nounwind ; CHECK: llvm_mips_binsl_d_test: -; CHECK: ld.d -; CHECK: ld.d -; CHECK: binsl.d -; CHECK: st.d +; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsl_d_ARG1)( +; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsl_d_ARG2)( +; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_binsl_d_ARG3)( +; CHECK-DAG: ld.d [[R4:\$w[0-9]+]], 0([[R1]]) +; CHECK-DAG: ld.d [[R5:\$w[0-9]+]], 0([[R2]]) +; CHECK-DAG: ld.d [[R6:\$w[0-9]+]], 0([[R3]]) +; CHECK-DAG: binsl.d [[R4]], [[R5]], [[R6]] +; CHECK-DAG: st.d [[R4]], 0( ; CHECK: .size llvm_mips_binsl_d_test -; + @llvm_mips_binsr_b_ARG1 = global <16 x i8> , align 16 -@llvm_mips_binsr_b_ARG2 = global <16 x i8> , align 16 +@llvm_mips_binsr_b_ARG2 = global <16 x i8> , align 16 +@llvm_mips_binsr_b_ARG3 = global <16 x i8> , align 16 @llvm_mips_binsr_b_RES = global <16 x i8> , align 16 define void @llvm_mips_binsr_b_test() nounwind { entry: %0 = load <16 x i8>* @llvm_mips_binsr_b_ARG1 %1 = load <16 x i8>* @llvm_mips_binsr_b_ARG2 - %2 = tail call <16 x i8> @llvm.mips.binsr.b(<16 x i8> %0, <16 x i8> %1) - store <16 x i8> %2, <16 x i8>* @llvm_mips_binsr_b_RES + %2 = load <16 x i8>* @llvm_mips_binsr_b_ARG3 + %3 = tail call <16 x i8> @llvm.mips.binsr.b(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2) + store <16 x i8> %3, <16 x i8>* @llvm_mips_binsr_b_RES ret void } -declare <16 x i8> @llvm.mips.binsr.b(<16 x i8>, <16 x i8>) nounwind +declare <16 x i8> @llvm.mips.binsr.b(<16 x i8>, <16 x i8>, <16 x i8>) nounwind ; CHECK: llvm_mips_binsr_b_test: -; CHECK: ld.b -; CHECK: ld.b -; CHECK: binsr.b -; CHECK: st.b +; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsr_b_ARG1)( +; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsr_b_ARG2)( +; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_binsr_b_ARG3)( +; CHECK-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R1]]) +; CHECK-DAG: ld.b [[R5:\$w[0-9]+]], 0([[R2]]) +; CHECK-DAG: ld.b [[R6:\$w[0-9]+]], 0([[R3]]) +; CHECK-DAG: binsr.b [[R4]], [[R5]], [[R6]] +; CHECK-DAG: st.b [[R4]], 0( ; CHECK: .size llvm_mips_binsr_b_test -; + @llvm_mips_binsr_h_ARG1 = global <8 x i16> , align 16 -@llvm_mips_binsr_h_ARG2 = global <8 x i16> , align 16 +@llvm_mips_binsr_h_ARG2 = global <8 x i16> , align 16 +@llvm_mips_binsr_h_ARG3 = global <8 x i16> , align 16 @llvm_mips_binsr_h_RES = global <8 x i16> , align 16 define void @llvm_mips_binsr_h_test() nounwind { entry: %0 = load <8 x i16>* @llvm_mips_binsr_h_ARG1 %1 = load <8 x i16>* @llvm_mips_binsr_h_ARG2 - %2 = tail call <8 x i16> @llvm.mips.binsr.h(<8 x i16> %0, <8 x i16> %1) - store <8 x i16> %2, <8 x i16>* @llvm_mips_binsr_h_RES + %2 = load <8 x i16>* @llvm_mips_binsr_h_ARG3 + %3 = tail call <8 x i16> @llvm.mips.binsr.h(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2) + store <8 x i16> %3, <8 x i16>* @llvm_mips_binsr_h_RES ret void } -declare <8 x i16> @llvm.mips.binsr.h(<8 x i16>, <8 x i16>) nounwind +declare <8 x i16> @llvm.mips.binsr.h(<8 x i16>, <8 x i16>, <8 x i16>) nounwind ; CHECK: llvm_mips_binsr_h_test: -; CHECK: ld.h -; CHECK: ld.h -; CHECK: binsr.h -; CHECK: st.h +; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsr_h_ARG1)( +; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsr_h_ARG2)( +; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_binsr_h_ARG3)( +; CHECK-DAG: ld.h [[R4:\$w[0-9]+]], 0([[R1]]) +; CHECK-DAG: ld.h [[R5:\$w[0-9]+]], 0([[R2]]) +; CHECK-DAG: ld.h [[R6:\$w[0-9]+]], 0([[R3]]) +; CHECK-DAG: binsr.h [[R4]], [[R5]], [[R6]] +; CHECK-DAG: st.h [[R4]], 0( ; CHECK: .size llvm_mips_binsr_h_test -; + @llvm_mips_binsr_w_ARG1 = global <4 x i32> , align 16 -@llvm_mips_binsr_w_ARG2 = global <4 x i32> , align 16 +@llvm_mips_binsr_w_ARG2 = global <4 x i32> , align 16 +@llvm_mips_binsr_w_ARG3 = global <4 x i32> , align 16 @llvm_mips_binsr_w_RES = global <4 x i32> , align 16 define void @llvm_mips_binsr_w_test() nounwind { entry: %0 = load <4 x i32>* @llvm_mips_binsr_w_ARG1 %1 = load <4 x i32>* @llvm_mips_binsr_w_ARG2 - %2 = tail call <4 x i32> @llvm.mips.binsr.w(<4 x i32> %0, <4 x i32> %1) - store <4 x i32> %2, <4 x i32>* @llvm_mips_binsr_w_RES + %2 = load <4 x i32>* @llvm_mips_binsr_w_ARG3 + %3 = tail call <4 x i32> @llvm.mips.binsr.w(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2) + store <4 x i32> %3, <4 x i32>* @llvm_mips_binsr_w_RES ret void } -declare <4 x i32> @llvm.mips.binsr.w(<4 x i32>, <4 x i32>) nounwind +declare <4 x i32> @llvm.mips.binsr.w(<4 x i32>, <4 x i32>, <4 x i32>) nounwind ; CHECK: llvm_mips_binsr_w_test: -; CHECK: ld.w -; CHECK: ld.w -; CHECK: binsr.w -; CHECK: st.w +; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsr_w_ARG1)( +; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsr_w_ARG2)( +; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_binsr_w_ARG3)( +; CHECK-DAG: ld.w [[R4:\$w[0-9]+]], 0([[R1]]) +; CHECK-DAG: ld.w [[R5:\$w[0-9]+]], 0([[R2]]) +; CHECK-DAG: ld.w [[R6:\$w[0-9]+]], 0([[R3]]) +; CHECK-DAG: binsr.w [[R4]], [[R5]], [[R6]] +; CHECK-DAG: st.w [[R4]], 0( ; CHECK: .size llvm_mips_binsr_w_test -; + @llvm_mips_binsr_d_ARG1 = global <2 x i64> , align 16 -@llvm_mips_binsr_d_ARG2 = global <2 x i64> , align 16 +@llvm_mips_binsr_d_ARG2 = global <2 x i64> , align 16 +@llvm_mips_binsr_d_ARG3 = global <2 x i64> , align 16 @llvm_mips_binsr_d_RES = global <2 x i64> , align 16 define void @llvm_mips_binsr_d_test() nounwind { entry: %0 = load <2 x i64>* @llvm_mips_binsr_d_ARG1 %1 = load <2 x i64>* @llvm_mips_binsr_d_ARG2 - %2 = tail call <2 x i64> @llvm.mips.binsr.d(<2 x i64> %0, <2 x i64> %1) - store <2 x i64> %2, <2 x i64>* @llvm_mips_binsr_d_RES + %2 = load <2 x i64>* @llvm_mips_binsr_d_ARG3 + %3 = tail call <2 x i64> @llvm.mips.binsr.d(<2 x i64> %0, <2 x i64> %1, <2 x i64> %2) + store <2 x i64> %3, <2 x i64>* @llvm_mips_binsr_d_RES ret void } -declare <2 x i64> @llvm.mips.binsr.d(<2 x i64>, <2 x i64>) nounwind +declare <2 x i64> @llvm.mips.binsr.d(<2 x i64>, <2 x i64>, <2 x i64>) nounwind ; CHECK: llvm_mips_binsr_d_test: -; CHECK: ld.d -; CHECK: ld.d -; CHECK: binsr.d -; CHECK: st.d +; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsr_d_ARG1)( +; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsr_d_ARG2)( +; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_binsr_d_ARG3)( +; CHECK-DAG: ld.d [[R4:\$w[0-9]+]], 0([[R1]]) +; CHECK-DAG: ld.d [[R5:\$w[0-9]+]], 0([[R2]]) +; CHECK-DAG: ld.d [[R6:\$w[0-9]+]], 0([[R3]]) +; CHECK-DAG: binsr.d [[R4]], [[R5]], [[R6]] +; CHECK-DAG: st.d [[R4]], 0( ; CHECK: .size llvm_mips_binsr_d_test -; + @llvm_mips_bneg_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_bneg_b_ARG2 = global <16 x i8> , align 16 @llvm_mips_bneg_b_RES = global <16 x i8> , align 16 -- cgit v1.2.3