From 152932b71c488a6522c541f847eb3081cffb3793 Mon Sep 17 00:00:00 2001 From: Rafael Espindola Date: Tue, 17 Mar 2009 23:43:59 +0000 Subject: Don't force promotion of return arguments on the callee. Some architectures (like x86) don't require it. This fixes bug 3779. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67132 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/CellSPU/and_ops.ll | 4 ++-- test/CodeGen/CellSPU/eqv.ll | 3 --- test/CodeGen/CellSPU/icmp16.ll | 2 +- test/CodeGen/CellSPU/immed16.ll | 2 +- test/CodeGen/CellSPU/nand.ll | 4 +--- test/CodeGen/CellSPU/or_ops.ll | 1 - test/CodeGen/CellSPU/shift_ops.ll | 2 -- test/CodeGen/CellSPU/stores.ll | 10 +++++----- test/CodeGen/CellSPU/struct_1.ll | 4 ---- test/CodeGen/X86/2007-08-10-SignExtSubreg.ll | 2 +- test/CodeGen/X86/20090313-signext.ll | 18 ++++++++++++++++++ test/CodeGen/X86/const-select.ll | 2 +- test/CodeGen/X86/isel-sink2.ll | 5 +++-- test/CodeGen/X86/sext-trunc.ll | 3 ++- test/CodeGen/X86/tls11.ll | 2 +- test/CodeGen/X86/tls12.ll | 2 +- 16 files changed, 37 insertions(+), 29 deletions(-) create mode 100644 test/CodeGen/X86/20090313-signext.ll (limited to 'test') diff --git a/test/CodeGen/CellSPU/and_ops.ll b/test/CodeGen/CellSPU/and_ops.ll index a18b6f8d05..cb066963b1 100644 --- a/test/CodeGen/CellSPU/and_ops.ll +++ b/test/CodeGen/CellSPU/and_ops.ll @@ -1,7 +1,7 @@ ; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s -; RUN: grep and %t1.s | count 234 +; RUN: grep and %t1.s | count 230 ; RUN: grep andc %t1.s | count 85 -; RUN: grep andi %t1.s | count 37 +; RUN: grep andi %t1.s | count 35 ; RUN: grep andhi %t1.s | count 30 ; RUN: grep andbi %t1.s | count 4 diff --git a/test/CodeGen/CellSPU/eqv.ll b/test/CodeGen/CellSPU/eqv.ll index 5406956772..a578315c6b 100644 --- a/test/CodeGen/CellSPU/eqv.ll +++ b/test/CodeGen/CellSPU/eqv.ll @@ -1,8 +1,5 @@ ; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s ; RUN: grep eqv %t1.s | count 18 -; RUN: grep xshw %t1.s | count 6 -; RUN: grep xsbh %t1.s | count 3 -; RUN: grep andi %t1.s | count 3 ; Test the 'eqv' instruction, whose boolean expression is: ; (a & b) | (~a & ~b), which simplifies to diff --git a/test/CodeGen/CellSPU/icmp16.ll b/test/CodeGen/CellSPU/icmp16.ll index 16bf0f9f62..56d1b8fb41 100644 --- a/test/CodeGen/CellSPU/icmp16.ll +++ b/test/CodeGen/CellSPU/icmp16.ll @@ -1,5 +1,5 @@ ; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s -; RUN: grep ilh %t1.s | count 5 +; RUN: grep ilh %t1.s | count 15 ; RUN: grep ceqh %t1.s | count 29 ; RUN: grep ceqhi %t1.s | count 13 ; RUN: grep clgth %t1.s | count 15 diff --git a/test/CodeGen/CellSPU/immed16.ll b/test/CodeGen/CellSPU/immed16.ll index 684305bd0c..9a461cbb85 100644 --- a/test/CodeGen/CellSPU/immed16.ll +++ b/test/CodeGen/CellSPU/immed16.ll @@ -1,5 +1,5 @@ ; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s -; RUN: grep "ilh" %t1.s | count 5 +; RUN: grep "ilh" %t1.s | count 11 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" target triple = "spu" diff --git a/test/CodeGen/CellSPU/nand.ll b/test/CodeGen/CellSPU/nand.ll index 841a3ec54d..ccbd5d90e5 100644 --- a/test/CodeGen/CellSPU/nand.ll +++ b/test/CodeGen/CellSPU/nand.ll @@ -1,8 +1,6 @@ ; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s ; RUN: grep nand %t1.s | count 90 -; RUN: grep and %t1.s | count 94 -; RUN: grep xsbh %t1.s | count 2 -; RUN: grep xshw %t1.s | count 4 +; RUN: grep and %t1.s | count 90 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" target triple = "spu" diff --git a/test/CodeGen/CellSPU/or_ops.ll b/test/CodeGen/CellSPU/or_ops.ll index 4e9da8f129..49e5ec36d2 100644 --- a/test/CodeGen/CellSPU/or_ops.ll +++ b/test/CodeGen/CellSPU/or_ops.ll @@ -1,5 +1,4 @@ ; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s -; RUN: grep and %t1.s | count 2 ; RUN: grep orc %t1.s | count 85 ; RUN: grep ori %t1.s | count 30 ; RUN: grep orhi %t1.s | count 30 diff --git a/test/CodeGen/CellSPU/shift_ops.ll b/test/CodeGen/CellSPU/shift_ops.ll index 3c26baa7c7..3b7dacd3cd 100644 --- a/test/CodeGen/CellSPU/shift_ops.ll +++ b/test/CodeGen/CellSPU/shift_ops.ll @@ -3,8 +3,6 @@ ; RUN: grep {shlhi } %t1.s | count 3 ; RUN: grep {shl } %t1.s | count 9 ; RUN: grep {shli } %t1.s | count 3 -; RUN: grep {xshw } %t1.s | count 5 -; RUN: grep {and } %t1.s | count 5 ; RUN: grep {andi } %t1.s | count 2 ; RUN: grep {rotmi } %t1.s | count 2 ; RUN: grep {rotqmbyi } %t1.s | count 1 diff --git a/test/CodeGen/CellSPU/stores.ll b/test/CodeGen/CellSPU/stores.ll index f2f35ef4db..f59bfd49ac 100644 --- a/test/CodeGen/CellSPU/stores.ll +++ b/test/CodeGen/CellSPU/stores.ll @@ -6,13 +6,13 @@ ; RUN: grep 771 %t1.s | count 4 ; RUN: grep 515 %t1.s | count 2 ; RUN: grep 1799 %t1.s | count 2 -; RUN: grep 1543 %t1.s | count 5 -; RUN: grep 1029 %t1.s | count 3 +; RUN: grep 1543 %t1.s | count 3 +; RUN: grep 1029 %t1.s | count 1 ; RUN: grep {shli.*, 4} %t1.s | count 4 ; RUN: grep stqx %t1.s | count 4 -; RUN: grep ilhu %t1.s | count 11 -; RUN: grep iohl %t1.s | count 8 -; RUN: grep shufb %t1.s | count 15 +; RUN: grep ilhu %t1.s | count 9 +; RUN: grep iohl %t1.s | count 6 +; RUN: grep shufb %t1.s | count 13 ; RUN: grep frds %t1.s | count 1 ; ModuleID = 'stores.bc' diff --git a/test/CodeGen/CellSPU/struct_1.ll b/test/CodeGen/CellSPU/struct_1.ll index 82d319dd10..260a7f4198 100644 --- a/test/CodeGen/CellSPU/struct_1.ll +++ b/test/CodeGen/CellSPU/struct_1.ll @@ -3,8 +3,6 @@ ; RUN: grep lqa %t1.s | count 5 ; RUN: grep lqd %t1.s | count 11 ; RUN: grep rotqbyi %t1.s | count 7 -; RUN: grep xshw %t1.s | count 1 -; RUN: grep andi %t1.s | count 5 ; RUN: grep cbd %t1.s | count 3 ; RUN: grep chd %t1.s | count 1 ; RUN: grep cwd %t1.s | count 3 @@ -14,8 +12,6 @@ ; RUN: grep ilhu %t2.s | count 16 ; RUN: grep lqd %t2.s | count 16 ; RUN: grep rotqbyi %t2.s | count 7 -; RUN: grep xshw %t2.s | count 1 -; RUN: grep andi %t2.s | count 5 ; RUN: grep cbd %t2.s | count 3 ; RUN: grep chd %t2.s | count 1 ; RUN: grep cwd %t2.s | count 3 diff --git a/test/CodeGen/X86/2007-08-10-SignExtSubreg.ll b/test/CodeGen/X86/2007-08-10-SignExtSubreg.ll index b62d2c61bb..ffb1e83a27 100644 --- a/test/CodeGen/X86/2007-08-10-SignExtSubreg.ll +++ b/test/CodeGen/X86/2007-08-10-SignExtSubreg.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=x86 | grep {movsbl} +; RUN: llvm-as < %s | llc -march=x86 | not grep {movsbl} @X = global i32 0 ; [#uses=1] diff --git a/test/CodeGen/X86/20090313-signext.ll b/test/CodeGen/X86/20090313-signext.ll new file mode 100644 index 0000000000..d41b245486 --- /dev/null +++ b/test/CodeGen/X86/20090313-signext.ll @@ -0,0 +1,18 @@ +; RUN: llvm-as < %s | llc -march=x86-64 > %t +; RUN: grep {movswl %ax, %edi} %t +; RUN: grep {movw x(%rip), %ax} %t + +@x = common global i16 0 + +define signext i16 @f() nounwind { +entry: + %0 = tail call signext i16 @h() nounwind + %1 = sext i16 %0 to i32 + tail call void @g(i32 %1) nounwind + %2 = load i16* @x, align 2 + ret i16 %2 +} + +declare signext i16 @h() + +declare void @g(i32) diff --git a/test/CodeGen/X86/const-select.ll b/test/CodeGen/X86/const-select.ll index 6e3156beb0..8cdf4ac22d 100644 --- a/test/CodeGen/X86/const-select.ll +++ b/test/CodeGen/X86/const-select.ll @@ -10,7 +10,7 @@ entry: ret float %iftmp.0.0 } -; RUN: llvm-as < %s | llc | grep {movsbl.*(%e.x,%e.x,4), %eax} +; RUN: llvm-as < %s | llc | grep {movb.*(%e.x,%e.x,4), %al} define signext i8 @test(i8* nocapture %P, double %F) nounwind readonly { entry: %0 = fcmp olt double %F, 4.200000e+01 ; [#uses=1] diff --git a/test/CodeGen/X86/isel-sink2.ll b/test/CodeGen/X86/isel-sink2.ll index d8e27e9aff..9d9c747fa4 100644 --- a/test/CodeGen/X86/isel-sink2.ll +++ b/test/CodeGen/X86/isel-sink2.ll @@ -1,5 +1,6 @@ -; RUN: llvm-as < %s | llc -march=x86 | grep {movzbl.7(%...)} -; RUN: llvm-as < %s | llc -march=x86 | not grep leal +; RUN: llvm-as < %s | llc -march=x86 > %t +; RUN: grep {movb.7(%...)} %t +; RUN: not grep leal %t define i8 @test(i32 *%P) nounwind { %Q = getelementptr i32* %P, i32 1 diff --git a/test/CodeGen/X86/sext-trunc.ll b/test/CodeGen/X86/sext-trunc.ll index 97b4666827..df401564c2 100644 --- a/test/CodeGen/X86/sext-trunc.ll +++ b/test/CodeGen/X86/sext-trunc.ll @@ -1,5 +1,6 @@ ; RUN: llvm-as < %s | llc -march=x86 > %t -; RUN: grep movsbl %t +; RUN: grep movb %t +; RUN: not grep movsbl %t ; RUN: not grep movz %t ; RUN: not grep and %t diff --git a/test/CodeGen/X86/tls11.ll b/test/CodeGen/X86/tls11.ll index 32d0a1204c..f8543c089f 100644 --- a/test/CodeGen/X86/tls11.ll +++ b/test/CodeGen/X86/tls11.ll @@ -1,5 +1,5 @@ ; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu > %t -; RUN: grep {movzwl %gs:i@NTPOFF, %eax} %t +; RUN: grep {movw %gs:i@NTPOFF, %ax} %t @i = thread_local global i16 15 diff --git a/test/CodeGen/X86/tls12.ll b/test/CodeGen/X86/tls12.ll index c6f766d447..17ea996aa4 100644 --- a/test/CodeGen/X86/tls12.ll +++ b/test/CodeGen/X86/tls12.ll @@ -1,5 +1,5 @@ ; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu > %t -; RUN: grep {movzbl %gs:i@NTPOFF, %eax} %t +; RUN: grep {movb %gs:i@NTPOFF, %al} %t @i = thread_local global i8 15 -- cgit v1.2.3