From 1dc335a79f5e899aacc6710dfe08ef20abb6a6c0 Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Mon, 20 Sep 2010 19:32:20 +0000 Subject: Simplify ARM callee-saved register handling by removing the distinction between the high and low registers for prologue/epilogue code. This was a Darwin-only thing that wasn't providing a realistic benefit anymore. Combining the save areas simplifies the compiler code and results in better ARM/Thumb2 codegen. For example, previously we would generate code like: push {r4, r5, r6, r7, lr} add r7, sp, #12 stmdb sp!, {r8, r10, r11} With this change, we combine the register saves and generate: push {r4, r5, r6, r7, r8, r10, r11, lr} add r7, sp, #12 rdar://8445635 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114340 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/ARM/lsr-code-insertion.ll | 2 +- test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll | 13 ++++++------- 2 files changed, 7 insertions(+), 8 deletions(-) (limited to 'test') diff --git a/test/CodeGen/ARM/lsr-code-insertion.ll b/test/CodeGen/ARM/lsr-code-insertion.ll index b8c543b1bd..9f1a44a5fe 100644 --- a/test/CodeGen/ARM/lsr-code-insertion.ll +++ b/test/CodeGen/ARM/lsr-code-insertion.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -stats |& grep {38.*Number of machine instrs printed} +; RUN: llc < %s -stats |& grep {36.*Number of machine instrs printed} ; RUN: llc < %s -stats |& not grep {.*Number of re-materialization} ; This test really wants to check that the resultant "cond_true" block only ; has a single store in it, and that cond_true55 only has code to materialize diff --git a/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll b/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll index f91e1c9feb..a0caf3b76a 100644 --- a/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll +++ b/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll @@ -32,15 +32,14 @@ define fastcc i32 @parse_percent_token() nounwind { entry: -; CHECK: ittt eq -; CHECK: ittt eq -; CHECK: ittt eq -; CHECK: ittt eq -; CHECK: ittt eq +; CHECK: itt eq +; CHECK: itt eq +; CHECK: itt eq +; CHECK: itt eq +; CHECK: itt eq ; CHECK: moveq r0 ; CHECK-NOT: LBB0_ -; CHECK: ldreq -; CHECK: popeq +; CHECK: ldmiaeq switch i32 undef, label %bb7 [ i32 37, label %bb43 i32 48, label %bb5 -- cgit v1.2.3