From 24e5f9652aff7fc28bb3855d12e9d7506b384ad6 Mon Sep 17 00:00:00 2001 From: Sasa Stankovic Date: Fri, 7 Feb 2014 17:16:40 +0000 Subject: [mips] Forbid the use of registers t6, t7 and t8 if the target is NaCl. Differential Revision: http://llvm-reviews.chandlerc.com/D2694 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200978 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/Mips/fastcc.ll | 13 +++++++++ test/CodeGen/Mips/nacl-reserved-regs.ll | 51 +++++++++++++++++++++++++++++++++ 2 files changed, 64 insertions(+) create mode 100644 test/CodeGen/Mips/nacl-reserved-regs.ll (limited to 'test') diff --git a/test/CodeGen/Mips/fastcc.ll b/test/CodeGen/Mips/fastcc.ll index 82919e7139..8ee7af88c6 100644 --- a/test/CodeGen/Mips/fastcc.ll +++ b/test/CodeGen/Mips/fastcc.ll @@ -1,4 +1,7 @@ ; RUN: llc < %s -march=mipsel | FileCheck %s +; RUN: llc < %s -mtriple=mipsel-none-nacl-gnu \ +; RUN: | FileCheck %s -check-prefix=CHECK-NACL + @gi0 = external global i32 @gi1 = external global i32 @@ -95,6 +98,11 @@ entry: ; CHECK: lw $5 ; CHECK: lw $4 +; t6, t7 and t8 are reserved in NaCl and cannot be used for fastcc. +; CHECK-NACL-NOT: lw $14 +; CHECK-NACL-NOT: lw $15 +; CHECK-NACL-NOT: lw $24 + %0 = load i32* @gi0, align 4 %1 = load i32* @gi1, align 4 %2 = load i32* @gi2, align 4 @@ -134,6 +142,11 @@ entry: ; CHECK: sw $24 ; CHECK: sw $3 +; t6, t7 and t8 are reserved in NaCl and cannot be used for fastcc. +; CHECK-NACL-NOT: sw $14 +; CHECK-NACL-NOT: sw $15 +; CHECK-NACL-NOT: sw $24 + store i32 %a0, i32* @g0, align 4 store i32 %a1, i32* @g1, align 4 store i32 %a2, i32* @g2, align 4 diff --git a/test/CodeGen/Mips/nacl-reserved-regs.ll b/test/CodeGen/Mips/nacl-reserved-regs.ll new file mode 100644 index 0000000000..ae21283b1f --- /dev/null +++ b/test/CodeGen/Mips/nacl-reserved-regs.ll @@ -0,0 +1,51 @@ +; RUN: llc -march=mipsel -O3 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-none-nacl-gnu -O3 < %s \ +; RUN: | FileCheck %s -check-prefix=CHECK-NACL + +@var = external global i32 + +define void @f() { + %val1 = load volatile i32* @var + %val2 = load volatile i32* @var + %val3 = load volatile i32* @var + %val4 = load volatile i32* @var + %val5 = load volatile i32* @var + %val6 = load volatile i32* @var + %val7 = load volatile i32* @var + %val8 = load volatile i32* @var + %val9 = load volatile i32* @var + %val10 = load volatile i32* @var + %val11 = load volatile i32* @var + %val12 = load volatile i32* @var + %val13 = load volatile i32* @var + %val14 = load volatile i32* @var + %val15 = load volatile i32* @var + %val16 = load volatile i32* @var + store volatile i32 %val1, i32* @var + store volatile i32 %val2, i32* @var + store volatile i32 %val3, i32* @var + store volatile i32 %val4, i32* @var + store volatile i32 %val5, i32* @var + store volatile i32 %val6, i32* @var + store volatile i32 %val7, i32* @var + store volatile i32 %val8, i32* @var + store volatile i32 %val9, i32* @var + store volatile i32 %val10, i32* @var + store volatile i32 %val11, i32* @var + store volatile i32 %val12, i32* @var + store volatile i32 %val13, i32* @var + store volatile i32 %val14, i32* @var + store volatile i32 %val15, i32* @var + store volatile i32 %val16, i32* @var + ret void + +; Check that t6, t7 and t8 are used in non-NaCl code. +; CHECK: lw $14 +; CHECK: lw $15 +; CHECK: lw $24 + +; t6, t7 and t8 are reserved in NaCl. +; CHECK-NACL-NOT: lw $14 +; CHECK-NACL-NOT: lw $15 +; CHECK-NACL-NOT: lw $24 +} -- cgit v1.2.3