From 2d0eef4c7dbd27ac63c2934a83235ea9f926f2eb Mon Sep 17 00:00:00 2001 From: Michael Kuperstein Date: Wed, 26 Feb 2014 12:06:36 +0000 Subject: Ensure bitcode encoding of instructions and their operands stays stable. This includes instructions with aggregate operands (insert/extract), instructions with vector operands (insert/extract/shuffle), binary arithmetic and bitwise instructions, conversion instructions and terminators. Work was done by lama.saba@intel.com. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202262 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/Bitcode/aggregateInstructions.3.2.ll | 33 +++++ test/Bitcode/aggregateInstructions.3.2.ll.bc | Bin 0 -> 452 bytes test/Bitcode/binaryFloatInstructions.3.2.ll | 120 +++++++++++++++++ test/Bitcode/binaryFloatInstructions.3.2.ll.bc | Bin 0 -> 992 bytes test/Bitcode/binaryIntInstructions.3.2.ll | 177 +++++++++++++++++++++++++ test/Bitcode/binaryIntInstructions.3.2.ll.bc | Bin 0 -> 1324 bytes test/Bitcode/bitwiseInstructions.3.2.ll | 68 ++++++++++ test/Bitcode/bitwiseInstructions.3.2.ll.bc | Bin 0 -> 612 bytes test/Bitcode/conversionInstructions.3.2.ll | 104 +++++++++++++++ test/Bitcode/conversionInstructions.3.2.ll.bc | Bin 0 -> 996 bytes test/Bitcode/terminatorInstructions.3.2.ll | 47 +++++++ test/Bitcode/terminatorInstructions.3.2.ll.bc | Bin 0 -> 568 bytes test/Bitcode/vectorInstructions.3.2.ll | 34 +++++ test/Bitcode/vectorInstructions.3.2.ll.bc | Bin 0 -> 500 bytes 14 files changed, 583 insertions(+) create mode 100644 test/Bitcode/aggregateInstructions.3.2.ll create mode 100644 test/Bitcode/aggregateInstructions.3.2.ll.bc create mode 100644 test/Bitcode/binaryFloatInstructions.3.2.ll create mode 100644 test/Bitcode/binaryFloatInstructions.3.2.ll.bc create mode 100644 test/Bitcode/binaryIntInstructions.3.2.ll create mode 100644 test/Bitcode/binaryIntInstructions.3.2.ll.bc create mode 100644 test/Bitcode/bitwiseInstructions.3.2.ll create mode 100644 test/Bitcode/bitwiseInstructions.3.2.ll.bc create mode 100644 test/Bitcode/conversionInstructions.3.2.ll create mode 100644 test/Bitcode/conversionInstructions.3.2.ll.bc create mode 100644 test/Bitcode/terminatorInstructions.3.2.ll create mode 100644 test/Bitcode/terminatorInstructions.3.2.ll.bc create mode 100644 test/Bitcode/vectorInstructions.3.2.ll create mode 100644 test/Bitcode/vectorInstructions.3.2.ll.bc (limited to 'test') diff --git a/test/Bitcode/aggregateInstructions.3.2.ll b/test/Bitcode/aggregateInstructions.3.2.ll new file mode 100644 index 0000000000..9352390b13 --- /dev/null +++ b/test/Bitcode/aggregateInstructions.3.2.ll @@ -0,0 +1,33 @@ +; RUN: llvm-dis < %s.bc| FileCheck %s + +; aggregateOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2. +; The test checks that LLVM does not misread instructions with aggregate operands +; in older bitcode files. + +define void @extractvalue([4 x i8] %x1, [4 x [4 x i8]] %x2, {{i32, float}} %x3){ +entry: +; CHECK: %res1 = extractvalue [4 x i8] %x1, 0 + %res1 = extractvalue [4 x i8] %x1, 0 + +; CHECK-NEXT: %res2 = extractvalue [4 x [4 x i8]] %x2, 1 + %res2 = extractvalue [4 x [4 x i8 ]] %x2, 1 + +; CHECK-NEXT: %res3 = extractvalue [4 x [4 x i8]] %x2, 0, 1 + %res3 = extractvalue [4 x [4 x i8 ]] %x2, 0, 1 + +; CHECK-NEXT: %res4 = extractvalue { { i32, float } } %x3, 0, 1 + %res4 = extractvalue {{i32, float}} %x3, 0, 1 + + ret void +} + +define void @insertvalue([4 x [4 x i8 ]] %x1){ +entry: +; CHECK: %res1 = insertvalue [4 x [4 x i8]] %x1, i8 0, 0, 0 + %res1 = insertvalue [4 x [4 x i8 ]] %x1, i8 0, 0, 0 + +; CHECK-NEXT: %res2 = insertvalue [4 x [4 x i8]] undef, i8 0, 0, 0 + %res2 = insertvalue [4 x [4 x i8 ]] undef, i8 0, 0, 0 + + ret void +} \ No newline at end of file diff --git a/test/Bitcode/aggregateInstructions.3.2.ll.bc b/test/Bitcode/aggregateInstructions.3.2.ll.bc new file mode 100644 index 0000000000..053f85fda6 Binary files /dev/null and b/test/Bitcode/aggregateInstructions.3.2.ll.bc differ diff --git a/test/Bitcode/binaryFloatInstructions.3.2.ll b/test/Bitcode/binaryFloatInstructions.3.2.ll new file mode 100644 index 0000000000..f94d82d23c --- /dev/null +++ b/test/Bitcode/binaryFloatInstructions.3.2.ll @@ -0,0 +1,120 @@ +; RUN: llvm-dis < %s.bc| FileCheck %s + +; BinaryFloatOperation.3.2.ll.bc was generated by passing this file to llvm-as-3.2. +; The test checks that LLVM does not misread binary float instructions from +; older bitcode files. + +define void @fadd(float %x1, double %x2 ,half %x3, fp128 %x4, x86_fp80 %x5, ppc_fp128 %x6){ +entry: +; CHECK: %res1 = fadd float %x1, %x1 + %res1 = fadd float %x1, %x1 + +; CHECK-NEXT: %res2 = fadd double %x2, %x2 + %res2 = fadd double %x2, %x2 + +; CHECK-NEXT: %res3 = fadd half %x3, %x3 + %res3 = fadd half %x3, %x3 + +; CHECK-NEXT: %res4 = fadd fp128 %x4, %x4 + %res4 = fadd fp128 %x4, %x4 + +; CHECK-NEXT: %res5 = fadd x86_fp80 %x5, %x5 + %res5 = fadd x86_fp80 %x5, %x5 + +; CHECK-NEXT: %res6 = fadd ppc_fp128 %x6, %x6 + %res6 = fadd ppc_fp128 %x6, %x6 + + ret void +} + +define void @faddFloatVec(<2 x float> %x1, <3 x float> %x2 ,<4 x float> %x3, <8 x float> %x4, <16 x float> %x5){ +entry: +; CHECK: %res1 = fadd <2 x float> %x1, %x1 + %res1 = fadd <2 x float> %x1, %x1 + +; CHECK-NEXT: %res2 = fadd <3 x float> %x2, %x2 + %res2 = fadd <3 x float> %x2, %x2 + +; CHECK-NEXT: %res3 = fadd <4 x float> %x3, %x3 + %res3 = fadd <4 x float> %x3, %x3 + +; CHECK-NEXT: %res4 = fadd <8 x float> %x4, %x4 + %res4 = fadd <8 x float> %x4, %x4 + +; CHECK-NEXT: %res5 = fadd <16 x float> %x5, %x5 + %res5 = fadd <16 x float> %x5, %x5 + + ret void +} + +define void @faddDoubleVec(<2 x double> %x1, <3 x double> %x2 ,<4 x double> %x3, <8 x double> %x4, <16 x double> %x5){ +entry: +; CHECK: %res1 = fadd <2 x double> %x1, %x1 + %res1 = fadd <2 x double> %x1, %x1 + +; CHECK-NEXT: %res2 = fadd <3 x double> %x2, %x2 + %res2 = fadd <3 x double> %x2, %x2 + +; CHECK-NEXT: %res3 = fadd <4 x double> %x3, %x3 + %res3 = fadd <4 x double> %x3, %x3 + +; CHECK-NEXT: %res4 = fadd <8 x double> %x4, %x4 + %res4 = fadd <8 x double> %x4, %x4 + +; CHECK-NEXT: %res5 = fadd <16 x double> %x5, %x5 + %res5 = fadd <16 x double> %x5, %x5 + + ret void +} + +define void @faddHalfVec(<2 x half> %x1, <3 x half> %x2 ,<4 x half> %x3, <8 x half> %x4, <16 x half> %x5){ +entry: +; CHECK: %res1 = fadd <2 x half> %x1, %x1 + %res1 = fadd <2 x half> %x1, %x1 + +; CHECK-NEXT: %res2 = fadd <3 x half> %x2, %x2 + %res2 = fadd <3 x half> %x2, %x2 + +; CHECK-NEXT: %res3 = fadd <4 x half> %x3, %x3 + %res3 = fadd <4 x half> %x3, %x3 + +; CHECK-NEXT: %res4 = fadd <8 x half> %x4, %x4 + %res4 = fadd <8 x half> %x4, %x4 + +; CHECK-NEXT: %res5 = fadd <16 x half> %x5, %x5 + %res5 = fadd <16 x half> %x5, %x5 + + ret void +} + +define void @fsub(float %x1){ +entry: +; CHECK: %res1 = fsub float %x1, %x1 + %res1 = fsub float %x1, %x1 + + ret void +} + +define void @fmul(float %x1){ +entry: +; CHECK: %res1 = fmul float %x1, %x1 + %res1 = fmul float %x1, %x1 + + ret void +} + +define void @fdiv(float %x1){ +entry: +; CHECK: %res1 = fdiv float %x1, %x1 + %res1 = fdiv float %x1, %x1 + + ret void +} + +define void @frem(float %x1){ +entry: +; CHECK: %res1 = frem float %x1, %x1 + %res1 = frem float %x1, %x1 + + ret void +} diff --git a/test/Bitcode/binaryFloatInstructions.3.2.ll.bc b/test/Bitcode/binaryFloatInstructions.3.2.ll.bc new file mode 100644 index 0000000000..8dbb4e456a Binary files /dev/null and b/test/Bitcode/binaryFloatInstructions.3.2.ll.bc differ diff --git a/test/Bitcode/binaryIntInstructions.3.2.ll b/test/Bitcode/binaryIntInstructions.3.2.ll new file mode 100644 index 0000000000..b08501ca93 --- /dev/null +++ b/test/Bitcode/binaryIntInstructions.3.2.ll @@ -0,0 +1,177 @@ +; RUN: llvm-dis < %s.bc| FileCheck %s + +; BinaryIntOperation.3.2.ll.bc was generated by passing this file to llvm-as-3.2. +; The test checks that LLVM does not misread binary integer instructions from +; older bitcode files. + +define void @add(i1 %x1, i8 %x2 ,i16 %x3, i32 %x4, i64 %x5){ +entry: +; CHECK: %res1 = add i1 %x1, %x1 + %res1 = add i1 %x1, %x1 + +; CHECK-NEXT: %res2 = add i8 %x2, %x2 + %res2 = add i8 %x2, %x2 + +; CHECK-NEXT: %res3 = add i16 %x3, %x3 + %res3 = add i16 %x3, %x3 + +; CHECK-NEXT: %res4 = add i32 %x4, %x4 + %res4 = add i32 %x4, %x4 + +; CHECK-NEXT: %res5 = add i64 %x5, %x5 + %res5 = add i64 %x5, %x5 + +; CHECK: %res6 = add nuw i1 %x1, %x1 + %res6 = add nuw i1 %x1, %x1 + +; CHECK: %res7 = add nsw i1 %x1, %x1 + %res7 = add nsw i1 %x1, %x1 + +; CHECK: %res8 = add nuw nsw i1 %x1, %x1 + %res8 = add nuw nsw i1 %x1, %x1 + + ret void +} + +define void @addvec8NuwNsw(<2 x i8> %x1, <3 x i8> %x2 ,<4 x i8> %x3, <8 x i8> %x4, <16 x i8> %x5){ +entry: +; CHECK: %res1 = add nuw nsw <2 x i8> %x1, %x1 + %res1 = add nuw nsw <2 x i8> %x1, %x1 + +; CHECK-NEXT: %res2 = add nuw nsw <3 x i8> %x2, %x2 + %res2 = add nuw nsw <3 x i8> %x2, %x2 + +; CHECK-NEXT: %res3 = add nuw nsw <4 x i8> %x3, %x3 + %res3 = add nuw nsw <4 x i8> %x3, %x3 + +; CHECK-NEXT: %res4 = add nuw nsw <8 x i8> %x4, %x4 + %res4 = add nuw nsw <8 x i8> %x4, %x4 + +; CHECK-NEXT: %res5 = add nuw nsw <16 x i8> %x5, %x5 + %res5 = add nuw nsw <16 x i8> %x5, %x5 + + ret void +} + +define void @addvec16NuwNsw(<2 x i16> %x1, <3 x i16> %x2 ,<4 x i16> %x3, <8 x i16> %x4, <16 x i16> %x5){ +entry: +; CHECK: %res1 = add nuw nsw <2 x i16> %x1, %x1 + %res1 = add nuw nsw <2 x i16> %x1, %x1 + +; CHECK-NEXT: %res2 = add nuw nsw <3 x i16> %x2, %x2 + %res2 = add nuw nsw <3 x i16> %x2, %x2 + +; CHECK-NEXT: %res3 = add nuw nsw <4 x i16> %x3, %x3 + %res3 = add nuw nsw <4 x i16> %x3, %x3 + +; CHECK-NEXT: %res4 = add nuw nsw <8 x i16> %x4, %x4 + %res4 = add nuw nsw <8 x i16> %x4, %x4 + +; CHECK-NEXT: %res5 = add nuw nsw <16 x i16> %x5, %x5 + %res5 = add nuw nsw <16 x i16> %x5, %x5 + + ret void +} + +define void @addvec32NuwNsw(<2 x i32> %x1, <3 x i32> %x2 ,<4 x i32> %x3, <8 x i32> %x4, <16 x i32> %x5){ +entry: +; CHECK: %res1 = add nuw nsw <2 x i32> %x1, %x1 + %res1 = add nuw nsw <2 x i32> %x1, %x1 + +; CHECK-NEXT: %res2 = add nuw nsw <3 x i32> %x2, %x2 + %res2 = add nuw nsw <3 x i32> %x2, %x2 + +; CHECK-NEXT: %res3 = add nuw nsw <4 x i32> %x3, %x3 + %res3 = add nuw nsw <4 x i32> %x3, %x3 + +; CHECK-NEXT: %res4 = add nuw nsw <8 x i32> %x4, %x4 + %res4 = add nuw nsw <8 x i32> %x4, %x4 + +; CHECK-NEXT: %res5 = add nuw nsw <16 x i32> %x5, %x5 + %res5 = add nuw nsw <16 x i32> %x5, %x5 + + ret void +} + +define void @addvec64NuwNsw(<2 x i64> %x1, <3 x i64> %x2 ,<4 x i64> %x3, <8 x i64> %x4, <16 x i64> %x5){ +entry: +; CHECK: %res1 = add nuw nsw <2 x i64> %x1, %x1 + %res1 = add nuw nsw <2 x i64> %x1, %x1 + +; CHECK-NEXT: %res2 = add nuw nsw <3 x i64> %x2, %x2 + %res2 = add nuw nsw <3 x i64> %x2, %x2 + +; CHECK-NEXT: %res3 = add nuw nsw <4 x i64> %x3, %x3 + %res3 = add nuw nsw <4 x i64> %x3, %x3 + +; CHECK-NEXT: %res4 = add nuw nsw <8 x i64> %x4, %x4 + %res4 = add nuw nsw <8 x i64> %x4, %x4 + +; CHECK-NEXT: %res5 = add nuw nsw <16 x i64> %x5, %x5 + %res5 = add nuw nsw <16 x i64> %x5, %x5 + + ret void +} + +define void @sub(i8 %x1){ +entry: +; CHECK: %res1 = sub i8 %x1, %x1 + %res1 = sub i8 %x1, %x1 + +; CHECK: %res2 = sub nuw i8 %x1, %x1 + %res2 = sub nuw i8 %x1, %x1 + +; CHECK: %res3 = sub nsw i8 %x1, %x1 + %res3 = sub nsw i8 %x1, %x1 + +; CHECK: %res4 = sub nuw nsw i8 %x1, %x1 + %res4 = sub nuw nsw i8 %x1, %x1 + + ret void +} + +define void @mul(i8 %x1){ +entry: +; CHECK: %res1 = mul i8 %x1, %x1 + %res1 = mul i8 %x1, %x1 + + ret void +} + +define void @udiv(i8 %x1){ +entry: +; CHECK: %res1 = udiv i8 %x1, %x1 + %res1 = udiv i8 %x1, %x1 + +; CHECK-NEXT: %res2 = udiv exact i8 %x1, %x1 + %res2 = udiv exact i8 %x1, %x1 + + ret void +} + +define void @sdiv(i8 %x1){ +entry: +; CHECK: %res1 = sdiv i8 %x1, %x1 + %res1 = sdiv i8 %x1, %x1 + +; CHECK-NEXT: %res2 = sdiv exact i8 %x1, %x1 + %res2 = sdiv exact i8 %x1, %x1 + + ret void +} + +define void @urem(i32 %x1){ +entry: +; CHECK: %res1 = urem i32 %x1, %x1 + %res1 = urem i32 %x1, %x1 + + ret void +} + +define void @srem(i32 %x1){ +entry: +; CHECK: %res1 = srem i32 %x1, %x1 + %res1 = srem i32 %x1, %x1 + + ret void +} diff --git a/test/Bitcode/binaryIntInstructions.3.2.ll.bc b/test/Bitcode/binaryIntInstructions.3.2.ll.bc new file mode 100644 index 0000000000..749e0c34dc Binary files /dev/null and b/test/Bitcode/binaryIntInstructions.3.2.ll.bc differ diff --git a/test/Bitcode/bitwiseInstructions.3.2.ll b/test/Bitcode/bitwiseInstructions.3.2.ll new file mode 100644 index 0000000000..6225a08f20 --- /dev/null +++ b/test/Bitcode/bitwiseInstructions.3.2.ll @@ -0,0 +1,68 @@ +; RUN: llvm-dis < %s.bc| FileCheck %s + +; bitwiseOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2. +; The test checks that LLVM does not misread bitwise instructions from +; older bitcode files. + +define void @shl(i8 %x1){ +entry: +; CHECK: %res1 = shl i8 %x1, %x1 + %res1 = shl i8 %x1, %x1 + +; CHECK: %res2 = shl nuw i8 %x1, %x1 + %res2 = shl nuw i8 %x1, %x1 + +; CHECK: %res3 = shl nsw i8 %x1, %x1 + %res3 = shl nsw i8 %x1, %x1 + +; CHECK: %res4 = shl nuw nsw i8 %x1, %x1 + %res4 = shl nuw nsw i8 %x1, %x1 + + ret void +} + +define void @lshr(i8 %x1){ +entry: +; CHECK: %res1 = lshr i8 %x1, %x1 + %res1 = lshr i8 %x1, %x1 + +; CHECK: %res2 = lshr exact i8 %x1, %x1 + %res2 = lshr exact i8 %x1, %x1 + + ret void +} + +define void @ashr(i8 %x1){ +entry: +; CHECK: %res1 = ashr i8 %x1, %x1 + %res1 = ashr i8 %x1, %x1 + +; CHECK-NEXT: %res2 = ashr exact i8 %x1, %x1 + %res2 = ashr exact i8 %x1, %x1 + + ret void +} + +define void @and(i8 %x1){ +entry: +; CHECK: %res1 = and i8 %x1, %x1 + %res1 = and i8 %x1, %x1 + + ret void +} + +define void @or(i8 %x1){ +entry: +; CHECK: %res1 = or i8 %x1, %x1 + %res1 = or i8 %x1, %x1 + + ret void +} + +define void @xor(i8 %x1){ +entry: +; CHECK: %res1 = xor i8 %x1, %x1 + %res1 = xor i8 %x1, %x1 + + ret void +} \ No newline at end of file diff --git a/test/Bitcode/bitwiseInstructions.3.2.ll.bc b/test/Bitcode/bitwiseInstructions.3.2.ll.bc new file mode 100644 index 0000000000..136a7c9a0a Binary files /dev/null and b/test/Bitcode/bitwiseInstructions.3.2.ll.bc differ diff --git a/test/Bitcode/conversionInstructions.3.2.ll b/test/Bitcode/conversionInstructions.3.2.ll new file mode 100644 index 0000000000..4b3f27386e --- /dev/null +++ b/test/Bitcode/conversionInstructions.3.2.ll @@ -0,0 +1,104 @@ +; RUN: llvm-dis < %s.bc| FileCheck %s + +; conversionOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2. +; The test checks that LLVM does not misread conversion instructions from +; older bitcode files. + +define void @trunc(i32 %src){ +entry: +; CHECK: %res1 = trunc i32 %src to i8 + %res1 = trunc i32 %src to i8 + + ret void +} + +define void @zext(i32 %src){ +entry: +; CHECK: %res1 = zext i32 %src to i64 + %res1 = zext i32 %src to i64 + + ret void +} + +define void @sext(i32 %src){ +entry: +; CHECK: %res1 = sext i32 %src to i64 + %res1 = sext i32 %src to i64 + + ret void +} + +define void @fptrunc(double %src){ +entry: +; CHECK: %res1 = fptrunc double %src to float + %res1 = fptrunc double %src to float + + ret void +} + +define void @fpext(float %src){ +entry: +; CHECK: %res1 = fpext float %src to double + %res1 = fpext float %src to double + + ret void +} + +define void @fptoui(float %src){ +entry: +; CHECK: %res1 = fptoui float %src to i32 + %res1 = fptoui float %src to i32 + + ret void +} + +define void @fptosi(float %src){ +entry: +; CHECK: %res1 = fptosi float %src to i32 + %res1 = fptosi float %src to i32 + + ret void +} + +define void @uitofp(i32 %src){ +entry: +; CHECK: %res1 = uitofp i32 %src to float + %res1 = uitofp i32 %src to float + + ret void +} + +define void @sitofp(i32 %src){ +entry: +; CHECK: %res1 = sitofp i32 %src to float + %res1 = sitofp i32 %src to float + + ret void +} + +define void @ptrtoint(i32* %src){ +entry: +; CHECK: %res1 = ptrtoint i32* %src to i8 + %res1 = ptrtoint i32* %src to i8 + + ret void +} + +define void @inttoptr(i32 %src){ +entry: +; CHECK: %res1 = inttoptr i32 %src to i32* + %res1 = inttoptr i32 %src to i32* + + ret void +} + +define void @bitcast(i32 %src1, i32* %src2){ +entry: +; CHECK: %res1 = bitcast i32 %src1 to i32 + %res1 = bitcast i32 %src1 to i32 + +; CHECK: %res2 = bitcast i32* %src2 to i64* + %res2 = bitcast i32* %src2 to i64* + + ret void +} \ No newline at end of file diff --git a/test/Bitcode/conversionInstructions.3.2.ll.bc b/test/Bitcode/conversionInstructions.3.2.ll.bc new file mode 100644 index 0000000000..fabf7dab6f Binary files /dev/null and b/test/Bitcode/conversionInstructions.3.2.ll.bc differ diff --git a/test/Bitcode/terminatorInstructions.3.2.ll b/test/Bitcode/terminatorInstructions.3.2.ll new file mode 100644 index 0000000000..31e78967ee --- /dev/null +++ b/test/Bitcode/terminatorInstructions.3.2.ll @@ -0,0 +1,47 @@ +; RUN: llvm-dis < %s.bc| FileCheck %s + +; TerminatorOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2. +; The test checks that LLVM does not misread terminator instructions from +; older bitcode files. + +define i32 @condbr(i1 %cond){ +entry: +; CHECK: br i1 %cond, label %TrueLabel, label %FalseLabel + br i1 %cond, label %TrueLabel, label %FalseLabel + + TrueLabel: + ret i32 1 + + FalseLabel: + ret i32 0 +} + +define i32 @uncondbr(){ +entry: +; CHECK: br label %uncondLabel + br label %uncondLabel + + uncondLabel: + ret i32 1 +} + +define i32 @indirectbr(i8* %Addr){ +entry: +; CHECK: indirectbr i8* %Addr, [label %bb1, label %bb2] + indirectbr i8* %Addr, [ label %bb1, label %bb2 ] + + bb1: + ret i32 1 + + bb2: + ret i32 0 +} + +define void @unreachable(){ +entry: +; CHECK: unreachable + unreachable + + ret void +} + diff --git a/test/Bitcode/terminatorInstructions.3.2.ll.bc b/test/Bitcode/terminatorInstructions.3.2.ll.bc new file mode 100644 index 0000000000..9d92ead8ad Binary files /dev/null and b/test/Bitcode/terminatorInstructions.3.2.ll.bc differ diff --git a/test/Bitcode/vectorInstructions.3.2.ll b/test/Bitcode/vectorInstructions.3.2.ll new file mode 100644 index 0000000000..b24ef75ef0 --- /dev/null +++ b/test/Bitcode/vectorInstructions.3.2.ll @@ -0,0 +1,34 @@ +; RUN: llvm-dis < %s.bc| FileCheck %s + +; vectorOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2. +; The test checks that LLVM does not misread vector operations of +; older bitcode files. + +define void @extractelement(<2 x i8> %x1){ +entry: +; CHECK: %res1 = extractelement <2 x i8> %x1, i32 0 + %res1 = extractelement <2 x i8> %x1, i32 0 + + ret void +} + +define void @insertelement(<2 x i8> %x1){ +entry: +; CHECK: %res1 = insertelement <2 x i8> %x1, i8 0, i32 0 + %res1 = insertelement <2 x i8> %x1, i8 0, i32 0 + + ret void +} + +define void @shufflevector(<2 x i8> %x1){ +entry: +; CHECK: %res1 = shufflevector <2 x i8> %x1, <2 x i8> %x1, <2 x i32> + %res1 = shufflevector <2 x i8> %x1, <2 x i8> %x1, <2 x i32> + +; CHECK-NEXT: %res2 = shufflevector <2 x i8> %x1, <2 x i8> undef, <2 x i32> + %res2 = shufflevector <2 x i8> %x1, <2 x i8> undef, <2 x i32> + + ret void +} + + diff --git a/test/Bitcode/vectorInstructions.3.2.ll.bc b/test/Bitcode/vectorInstructions.3.2.ll.bc new file mode 100644 index 0000000000..b172703170 Binary files /dev/null and b/test/Bitcode/vectorInstructions.3.2.ll.bc differ -- cgit v1.2.3