From 3ff3a8aa7511bede13e836303a083af37fec4f4e Mon Sep 17 00:00:00 2001 From: Jiangning Liu Date: Tue, 5 Nov 2013 17:42:05 +0000 Subject: Implement AArch64 Neon Crypto instruction classes AES, SHA, and 3 SHA. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194085 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/AArch64/neon-crypto.ll | 147 ++++++++++++++++++++++++++++++++++++ test/MC/AArch64/neon-crypto.s | 42 +++++++++++ test/MC/AArch64/neon-diagnostics.s | 106 ++++++++++++++++++++++++++ 3 files changed, 295 insertions(+) create mode 100644 test/CodeGen/AArch64/neon-crypto.ll create mode 100644 test/MC/AArch64/neon-crypto.s (limited to 'test') diff --git a/test/CodeGen/AArch64/neon-crypto.ll b/test/CodeGen/AArch64/neon-crypto.ll new file mode 100644 index 0000000000..e4ae22786d --- /dev/null +++ b/test/CodeGen/AArch64/neon-crypto.ll @@ -0,0 +1,147 @@ +; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s + +declare <4 x i32> @llvm.arm.neon.sha256su1.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) #1 + +declare <4 x i32> @llvm.arm.neon.sha256h2.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) #1 + +declare <4 x i32> @llvm.arm.neon.sha256h.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) #1 + +declare <4 x i32> @llvm.arm.neon.sha1su0.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) #1 + +declare <4 x i32> @llvm.aarch64.neon.sha1m(<4 x i32>, <1 x i32>, <4 x i32>) #1 + +declare <4 x i32> @llvm.aarch64.neon.sha1p(<4 x i32>, <1 x i32>, <4 x i32>) #1 + +declare <4 x i32> @llvm.aarch64.neon.sha1c(<4 x i32>, <1 x i32>, <4 x i32>) #1 + +declare <4 x i32> @llvm.arm.neon.sha256su0.v4i32(<4 x i32>, <4 x i32>) #1 + +declare <4 x i32> @llvm.arm.neon.sha1su1.v4i32(<4 x i32>, <4 x i32>) #1 + +declare <1 x i32> @llvm.arm.neon.sha1h.v1i32(<1 x i32>) #1 + +declare <16 x i8> @llvm.arm.neon.aesimc.v16i8(<16 x i8>) #1 + +declare <16 x i8> @llvm.arm.neon.aesmc.v16i8(<16 x i8>) #1 + +declare <16 x i8> @llvm.arm.neon.aesd.v16i8(<16 x i8>, <16 x i8>) #1 + +declare <16 x i8> @llvm.arm.neon.aese.v16i8(<16 x i8>, <16 x i8>) #1 + +define <16 x i8> @test_vaeseq_u8(<16 x i8> %data, <16 x i8> %key) { +; CHECK: test_vaeseq_u8: +; CHECK: aese {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +entry: + %aese.i = tail call <16 x i8> @llvm.arm.neon.aese.v16i8(<16 x i8> %data, <16 x i8> %key) + ret <16 x i8> %aese.i +} + +define <16 x i8> @test_vaesdq_u8(<16 x i8> %data, <16 x i8> %key) { +; CHECK: test_vaesdq_u8: +; CHECK: aesd {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +entry: + %aesd.i = tail call <16 x i8> @llvm.arm.neon.aesd.v16i8(<16 x i8> %data, <16 x i8> %key) + ret <16 x i8> %aesd.i +} + +define <16 x i8> @test_vaesmcq_u8(<16 x i8> %data) { +; CHECK: test_vaesmcq_u8: +; CHECK: aesmc {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +entry: + %aesmc.i = tail call <16 x i8> @llvm.arm.neon.aesmc.v16i8(<16 x i8> %data) + ret <16 x i8> %aesmc.i +} + +define <16 x i8> @test_vaesimcq_u8(<16 x i8> %data) { +; CHECK: test_vaesimcq_u8: +; CHECK: aesimc {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +entry: + %aesimc.i = tail call <16 x i8> @llvm.arm.neon.aesimc.v16i8(<16 x i8> %data) + ret <16 x i8> %aesimc.i +} + +define i32 @test_vsha1h_u32(i32 %hash_e) { +; CHECK: test_vsha1h_u32: +; CHECK: sha1h {{s[0-9]+}}, {{s[0-9]+}} +entry: + %sha1h.i = insertelement <1 x i32> undef, i32 %hash_e, i32 0 + %sha1h1.i = tail call <1 x i32> @llvm.arm.neon.sha1h.v1i32(<1 x i32> %sha1h.i) + %0 = extractelement <1 x i32> %sha1h1.i, i32 0 + ret i32 %0 +} + +define <4 x i32> @test_vsha1su1q_u32(<4 x i32> %tw0_3, <4 x i32> %w12_15) { +; CHECK: test_vsha1su1q_u32: +; CHECK: sha1su1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s +entry: + %sha1su12.i = tail call <4 x i32> @llvm.arm.neon.sha1su1.v4i32(<4 x i32> %tw0_3, <4 x i32> %w12_15) + ret <4 x i32> %sha1su12.i +} + +define <4 x i32> @test_vsha256su0q_u32(<4 x i32> %w0_3, <4 x i32> %w4_7) { +; CHECK: test_vsha256su0q_u32: +; CHECK: sha256su0 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s +entry: + %sha256su02.i = tail call <4 x i32> @llvm.arm.neon.sha256su0.v4i32(<4 x i32> %w0_3, <4 x i32> %w4_7) + ret <4 x i32> %sha256su02.i +} + +define <4 x i32> @test_vsha1cq_u32(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) { +; CHECK: test_vsha1cq_u32: +; CHECK: sha1c {{q[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.4s +entry: + %sha1c.i = insertelement <1 x i32> undef, i32 %hash_e, i32 0 + %sha1c1.i = tail call <4 x i32> @llvm.aarch64.neon.sha1c(<4 x i32> %hash_abcd, <1 x i32> %sha1c.i, <4 x i32> %wk) + ret <4 x i32> %sha1c1.i +} + +define <4 x i32> @test_vsha1pq_u32(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) { +; CHECK: test_vsha1pq_u32: +; CHECK: sha1p {{q[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.4s +entry: + %sha1p.i = insertelement <1 x i32> undef, i32 %hash_e, i32 0 + %sha1p1.i = tail call <4 x i32> @llvm.aarch64.neon.sha1p(<4 x i32> %hash_abcd, <1 x i32> %sha1p.i, <4 x i32> %wk) + ret <4 x i32> %sha1p1.i +} + +define <4 x i32> @test_vsha1mq_u32(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) { +; CHECK: test_vsha1mq_u32: +; CHECK: sha1m {{q[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.4s +entry: + %sha1m.i = insertelement <1 x i32> undef, i32 %hash_e, i32 0 + %sha1m1.i = tail call <4 x i32> @llvm.aarch64.neon.sha1m(<4 x i32> %hash_abcd, <1 x i32> %sha1m.i, <4 x i32> %wk) + ret <4 x i32> %sha1m1.i +} + +define <4 x i32> @test_vsha1su0q_u32(<4 x i32> %w0_3, <4 x i32> %w4_7, <4 x i32> %w8_11) { +; CHECK: test_vsha1su0q_u32: +; CHECK: sha1su0 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s +entry: + %sha1su03.i = tail call <4 x i32> @llvm.arm.neon.sha1su0.v4i32(<4 x i32> %w0_3, <4 x i32> %w4_7, <4 x i32> %w8_11) + ret <4 x i32> %sha1su03.i +} + +define <4 x i32> @test_vsha256hq_u32(<4 x i32> %hash_abcd, <4 x i32> %hash_efgh, <4 x i32> %wk) { +; CHECK: test_vsha256hq_u32: +; CHECK: sha256h {{q[0-9]+}}, {{q[0-9]+}}, {{v[0-9]+}}.4s +entry: + %sha256h3.i = tail call <4 x i32> @llvm.arm.neon.sha256h.v4i32(<4 x i32> %hash_abcd, <4 x i32> %hash_efgh, <4 x i32> %wk) + ret <4 x i32> %sha256h3.i +} + +define <4 x i32> @test_vsha256h2q_u32(<4 x i32> %hash_efgh, <4 x i32> %hash_abcd, <4 x i32> %wk) { +; CHECK: test_vsha256h2q_u32: +; CHECK: sha256h2 {{q[0-9]+}}, {{q[0-9]+}}, {{v[0-9]+}}.4s +entry: + %sha256h23.i = tail call <4 x i32> @llvm.arm.neon.sha256h2.v4i32(<4 x i32> %hash_efgh, <4 x i32> %hash_abcd, <4 x i32> %wk) + ret <4 x i32> %sha256h23.i +} + +define <4 x i32> @test_vsha256su1q_u32(<4 x i32> %tw0_3, <4 x i32> %w8_11, <4 x i32> %w12_15) { +; CHECK: test_vsha256su1q_u32: +; CHECK: sha256su1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s +entry: + %sha256su13.i = tail call <4 x i32> @llvm.arm.neon.sha256su1.v4i32(<4 x i32> %tw0_3, <4 x i32> %w8_11, <4 x i32> %w12_15) + ret <4 x i32> %sha256su13.i +} + diff --git a/test/MC/AArch64/neon-crypto.s b/test/MC/AArch64/neon-crypto.s new file mode 100644 index 0000000000..df6eee851d --- /dev/null +++ b/test/MC/AArch64/neon-crypto.s @@ -0,0 +1,42 @@ +// RUN: llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + +//------------------------------------------------------------------------------ +// Instructions for crypto +//------------------------------------------------------------------------------ + + aese v0.16b, v1.16b + aesd v0.16b, v1.16b + aesmc v0.16b, v1.16b + aesimc v0.16b, v1.16b + +// CHECK: aese v0.16b, v1.16b // encoding: [0x20,0x48,0x28,0x4e] +// CHECK: aesd v0.16b, v1.16b // encoding: [0x20,0x58,0x28,0x4e] +// CHECK: aesmc v0.16b, v1.16b // encoding: [0x20,0x68,0x28,0x4e] +// CHECK: aesimc v0.16b, v1.16b // encoding: [0x20,0x78,0x28,0x4e] + + sha1h s0, s1 + sha1su1 v0.4s, v1.4s + sha256su0 v0.4s, v1.4s + +// CHECK: sha1h s0, s1 // encoding: [0x20,0x08,0x28,0x5e] +// CHECK: sha1su1 v0.4s, v1.4s // encoding: [0x20,0x18,0x28,0x5e] +// CHECK: sha256su0 v0.4s, v1.4s // encoding: [0x20,0x28,0x28,0x5e] + + sha1c q0, s1, v2.4s + sha1p q0, s1, v2.4s + sha1m q0, s1, v2.4s + sha1su0 v0.4s, v1.4s, v2.4s + sha256h q0, q1, v2.4s + sha256h2 q0, q1, v2.4s + sha256su1 v0.4s, v1.4s, v2.4s + +// CHECK: sha1c q0, s1, v2.4s // encoding: [0x20,0x00,0x02,0x5e] +// CHECK: sha1p q0, s1, v2.4s // encoding: [0x20,0x10,0x02,0x5e] +// CHECK: sha1m q0, s1, v2.4s // encoding: [0x20,0x20,0x02,0x5e] +// CHECK: sha1su0 v0.4s, v1.4s, v2.4s // encoding: [0x20,0x30,0x02,0x5e] +// CHECK: sha256h q0, q1, v2.4s // encoding: [0x20,0x40,0x02,0x5e] +// CHECK: sha256h2 q0, q1, v2.4s // encoding: [0x20,0x50,0x02,0x5e] +// CHECK: sha256su1 v0.4s, v1.4s, v2.4s // encoding: [0x20,0x60,0x02,0x5e] + diff --git a/test/MC/AArch64/neon-diagnostics.s b/test/MC/AArch64/neon-diagnostics.s index a43287d94b..67a938ed77 100644 --- a/test/MC/AArch64/neon-diagnostics.s +++ b/test/MC/AArch64/neon-diagnostics.s @@ -5088,3 +5088,109 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: ucvtf d21, s14, #64 // CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Unsigned Saturating Extract Narrow +//---------------------------------------------------------------------- + + aese v0.8h, v1.8h + aese v0.4s, v1.4s + aese v0.2d, v1.2d + aesd v0.8h, v1.8h + aesmc v0.8h, v1.8h + aesimc v0.8h, v1.8h + +// CHECK: error: invalid operand for instruction +// CHECK: aese v0.8h, v1.8h +// CHECK: ^ +// CHECK: error: invalid operand for instruction +// CHECK: aese v0.4s, v1.4s +// CHECK: ^ +// CHECK: error: invalid operand for instruction +// CHECK: aese v0.2d, v1.2d +// CHECK: ^ +// CHECK: error: invalid operand for instruction +// CHECK: aesd v0.8h, v1.8h +// CHECK: ^ +// CHECK: error: invalid operand for instruction +// CHECK: aesmc v0.8h, v1.8h +// CHECK: ^ +// CHECK: error: invalid operand for instruction +// CHECK: aesimc v0.8h, v1.8h +// CHECK: ^ + + sha1h b0, b1 + sha1h h0, h1 + sha1h d0, d1 + sha1h q0, q1 + sha1su1 v0.16b, v1.16b + sha1su1 v0.8h, v1.8h + sha1su1 v0.2d, v1.2d + sha256su0 v0.16b, v1.16b + +// CHECK: error: invalid operand for instruction +// CHECK: sha1h b0, b1 +// CHECK: ^ +// CHECK: error: invalid operand for instruction +// CHECK: sha1h h0, h1 +// CHECK: ^ +// CHECK: error: invalid operand for instruction +// CHECK: sha1h d0, d1 +// CHECK: ^ +// CHECK: error: invalid operand for instruction +// CHECK: sha1h q0, q1 +// CHECK: ^ +// CHECK: error: invalid operand for instruction +// CHECK: sha1su1 v0.16b, v1.16b +// CHECK: ^ +// CHECK: error: invalid operand for instruction +// CHECK: sha1su1 v0.8h, v1.8h +// CHECK: ^ +// CHECK: error: invalid operand for instruction +// CHECK: sha1su1 v0.2d, v1.2d +// CHECK: ^ +// CHECK: error: invalid operand for instruction +// CHECK: sha256su0 v0.16b, v1.16b +// CHECK: ^ + + sha1c q0, q1, v2.4s + sha1p q0, q1, v2.4s + sha1m q0, q1, v2.4s + sha1su0 v0.16b, v1.16b, v2.16b + sha1su0 v0.8h, v1.8h, v2.8h + sha1su0 v0.2d, v1.2d, v2.2d + sha256h q0, q1, q2 + sha256h v0.4s, v1.4s, v2.4s + sha256h2 q0, q1, q2 + sha256su1 v0.16b, v1.16b, v2.16b + +// CHECK: error: invalid operand for instruction +// CHECK: sha1c q0, q1, v2.4s +// CHECK: ^ +// CHECK: error: invalid operand for instruction +// CHECK: sha1p q0, q1, v2.4s +// CHECK: ^ +// CHECK: error: invalid operand for instruction +// CHECK: sha1m q0, q1, v2.4s +// CHECK: ^ +// CHECK: error: invalid operand for instruction +// CHECK: sha1su0 v0.16b, v1.16b, v2.16b +// CHECK: ^ +// CHECK: error: invalid operand for instruction +// CHECK: sha1su0 v0.8h, v1.8h, v2.8h +// CHECK: ^ +// CHECK: error: invalid operand for instruction +// CHECK: sha1su0 v0.2d, v1.2d, v2.2d +// CHECK: ^ +// CHECK: error: too few operands for instruction +// CHECK: sha256h q0, q1, q2 +// CHECK: ^ +// CHECK: error: invalid operand for instruction +// CHECK: sha256h v0.4s, v1.4s, v2.4s +// CHECK: ^ +// CHECK: error: too few operands for instruction +// CHECK: sha256h2 q0, q1, q2 +// CHECK: ^ +// CHECK: error: invalid operand for instruction +// CHECK: sha256su1 v0.16b, v1.16b, v2.16b +// CHECK: ^ -- cgit v1.2.3