From 591c2f738a3e12026ff5504a486d54fc21fb3049 Mon Sep 17 00:00:00 2001 From: Hao Liu Date: Tue, 5 Nov 2013 03:39:32 +0000 Subject: Implement AArch64 post-index vector load/store multiple N-element structure class SIMD(lselem-post). Including following 14 instructions: 4 ld1 insts: post-index load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: post-index load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: post-index store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: post-index store multiple N-element structure from sequential N registers (N = 2,3,4). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194043 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../AArch64/neon-simd-post-ldst-multi-elem.ll | 200 +++++++++++ test/MC/AArch64/neon-diagnostics.s | 56 +++ test/MC/AArch64/neon-simd-post-ldst-multi-elem.s | 389 +++++++++++++++++++++ test/MC/Disassembler/AArch64/neon-instructions.txt | 73 +++- 4 files changed, 717 insertions(+), 1 deletion(-) create mode 100644 test/CodeGen/AArch64/neon-simd-post-ldst-multi-elem.ll create mode 100644 test/MC/AArch64/neon-simd-post-ldst-multi-elem.s (limited to 'test') diff --git a/test/CodeGen/AArch64/neon-simd-post-ldst-multi-elem.ll b/test/CodeGen/AArch64/neon-simd-post-ldst-multi-elem.ll new file mode 100644 index 0000000000..5dd0aa88ec --- /dev/null +++ b/test/CodeGen/AArch64/neon-simd-post-ldst-multi-elem.ll @@ -0,0 +1,200 @@ +; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s + +define <4 x i16> @test_vld1_fx_update(i16** %ptr) nounwind { +; CHECK: test_vld1_fx_update +; CHECK: ld1 {v{{[0-9]+}}.4h}, [x{{[0-9]+|sp}}], #8 + %A = load i16** %ptr + %tmp0 = bitcast i16* %A to i8* + %tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16(i8* %tmp0, i32 2) + %tmp2 = getelementptr i16* %A, i32 4 + store i16* %tmp2, i16** %ptr + ret <4 x i16> %tmp1 +} + +define <2 x i32> @test_vld1_reg_update(i32** %ptr, i32 %inc) nounwind { +; CHECK: test_vld1_reg_update +; CHECK: ld1 {v{{[0-9]+}}.2s}, [x{{[0-9]+|sp}}], x{{[0-9]+}} + %A = load i32** %ptr + %tmp0 = bitcast i32* %A to i8* + %tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32(i8* %tmp0, i32 4) + %tmp2 = getelementptr i32* %A, i32 %inc + store i32* %tmp2, i32** %ptr + ret <2 x i32> %tmp1 +} + +define <2 x float> @test_vld2_fx_update(float** %ptr) nounwind { +; CHECK: test_vld2_fx_update +; CHECK: ld2 {v{{[0-9]+}}.2s, v{{[0-9]+}}.2s}, [x{{[0-9]+|sp}}], #16 + %A = load float** %ptr + %tmp0 = bitcast float* %A to i8* + %tmp1 = call { <2 x float>, <2 x float> } @llvm.arm.neon.vld2.v2f32(i8* %tmp0, i32 4) + %tmp2 = extractvalue { <2 x float>, <2 x float> } %tmp1, 0 + %tmp3 = getelementptr float* %A, i32 4 + store float* %tmp3, float** %ptr + ret <2 x float> %tmp2 +} + +define <16 x i8> @test_vld2_reg_update(i8** %ptr, i32 %inc) nounwind { +; CHECK: test_vld2_reg_update +; CHECK: ld2 {v{{[0-9]+}}.16b, v{{[0-9]+}}.16b}, [x{{[0-9]+|sp}}], x{{[0-9]+}} + %A = load i8** %ptr + %tmp0 = call { <16 x i8>, <16 x i8> } @llvm.arm.neon.vld2.v16i8(i8* %A, i32 1) + %tmp1 = extractvalue { <16 x i8>, <16 x i8> } %tmp0, 0 + %tmp2 = getelementptr i8* %A, i32 %inc + store i8* %tmp2, i8** %ptr + ret <16 x i8> %tmp1 +} + +define <4 x i32> @test_vld3_fx_update(i32** %ptr) nounwind { +; CHECK: test_vld3_fx_update +; CHECK: ld3 {v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s}, [x{{[0-9]+|sp}}], #48 + %A = load i32** %ptr + %tmp0 = bitcast i32* %A to i8* + %tmp1 = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm.neon.vld3.v4i32(i8* %tmp0, i32 4) + %tmp2 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %tmp1, 0 + %tmp3 = getelementptr i32* %A, i32 12 + store i32* %tmp3, i32** %ptr + ret <4 x i32> %tmp2 +} + +define <4 x i16> @test_vld3_reg_update(i16** %ptr, i32 %inc) nounwind { +; CHECK: test_vld3_reg_update +; CHECK: ld3 {v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h}, [x{{[0-9]+|sp}}], x{{[0-9]+}} + %A = load i16** %ptr + %tmp0 = bitcast i16* %A to i8* + %tmp1 = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld3.v4i16(i8* %tmp0, i32 2) + %tmp2 = extractvalue { <4 x i16>, <4 x i16>, <4 x i16> } %tmp1, 0 + %tmp3 = getelementptr i16* %A, i32 %inc + store i16* %tmp3, i16** %ptr + ret <4 x i16> %tmp2 +} + +define <8 x i16> @test_vld4_fx_update(i16** %ptr) nounwind { +; CHECK: test_vld4_fx_update +; CHECK: ld4 {v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h}, [x{{[0-9]+|sp}}], #64 + %A = load i16** %ptr + %tmp0 = bitcast i16* %A to i8* + %tmp1 = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld4.v8i16(i8* %tmp0, i32 8) + %tmp2 = extractvalue { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } %tmp1, 0 + %tmp3 = getelementptr i16* %A, i32 32 + store i16* %tmp3, i16** %ptr + ret <8 x i16> %tmp2 +} + +;Check for a post-increment updating load with register increment. +define <8 x i8> @test_vld4_reg_update(i8** %ptr, i32 %inc) nounwind { +; CHECK: test_vld4_reg_update +; CHECK: ld4 {v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b}, [x{{[0-9]+|sp}}], x{{[0-9]+}} + %A = load i8** %ptr + %tmp0 = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm.neon.vld4.v8i8(i8* %A, i32 1) + %tmp1 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %tmp0, 0 + %tmp2 = getelementptr i8* %A, i32 %inc + store i8* %tmp2, i8** %ptr + ret <8 x i8> %tmp1 +} + +;Check for a post-increment updating store. +define void @test_vst1_fx_update(float** %ptr, <2 x float> %B) nounwind { +; CHECK: test_vst1_fx_update +; CHECK: st1 {v{{[0-9]+}}.2s}, [{{x[0-9]+|sp}}], #8 + %A = load float** %ptr + %tmp0 = bitcast float* %A to i8* + call void @llvm.arm.neon.vst1.v2f32(i8* %tmp0, <2 x float> %B, i32 4) + %tmp2 = getelementptr float* %A, i32 2 + store float* %tmp2, float** %ptr + ret void +} + +define void @test_vst1_reg_update(i16** %ptr, <8 x i16> %B, i32 %inc) nounwind { +; CHECK: test_vst1_reg_update +; CHECK: st1 {v{{[0-9]+}}.8h}, [{{x[0-9]+|sp}}], x{{[0-9]+}} + %A = load i16** %ptr + %tmp0 = bitcast i16* %A to i8* + call void @llvm.arm.neon.vst1.v8i16(i8* %tmp0, <8 x i16> %B, i32 2) + %tmp1 = getelementptr i16* %A, i32 %inc + store i16* %tmp1, i16** %ptr + ret void +} + +define void @test_vst2_fx_update(i64** %ptr, <1 x i64> %B) nounwind { +; CHECK: test_vst2_fx_update +; CHECK: st1 {v{{[0-9]+}}.1d, v{{[0-9]+}}.1d}, [{{x[0-9]+|sp}}], #16 + %A = load i64** %ptr + %tmp0 = bitcast i64* %A to i8* + call void @llvm.arm.neon.vst2.v1i64(i8* %tmp0, <1 x i64> %B, <1 x i64> %B, i32 8) + %tmp1 = getelementptr i64* %A, i32 2 + store i64* %tmp1, i64** %ptr + ret void +} + +define void @test_vst2_reg_update(i8** %ptr, <8 x i8> %B, i32 %inc) nounwind { +; CHECK: test_vst2_reg_update +; CHECK: st2 {v{{[0-9]+}}.8b, v{{[0-9]+}}.8b}, [{{x[0-9]+|sp}}], x{{[0-9]+}} + %A = load i8** %ptr + call void @llvm.arm.neon.vst2.v8i8(i8* %A, <8 x i8> %B, <8 x i8> %B, i32 4) + %tmp0 = getelementptr i8* %A, i32 %inc + store i8* %tmp0, i8** %ptr + ret void +} + +define void @test_vst3_fx_update(i32** %ptr, <2 x i32> %B) nounwind { +; CHECK: test_vst3_fx_update +; CHECK: st3 {v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s}, [{{x[0-9]+|sp}}], #24 + %A = load i32** %ptr + %tmp0 = bitcast i32* %A to i8* + call void @llvm.arm.neon.vst3.v2i32(i8* %tmp0, <2 x i32> %B, <2 x i32> %B, <2 x i32> %B, i32 4) + %tmp1 = getelementptr i32* %A, i32 6 + store i32* %tmp1, i32** %ptr + ret void +} + +define void @test_vst3_reg_update(i16** %ptr, <8 x i16> %B, i32 %inc) nounwind { +; CHECK: test_vst3_reg_update +; CHECK: st3 {v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h}, [{{x[0-9]+|sp}}], x{{[0-9]+}} + %A = load i16** %ptr + %tmp0 = bitcast i16* %A to i8* + call void @llvm.arm.neon.vst3.v8i16(i8* %tmp0, <8 x i16> %B, <8 x i16> %B, <8 x i16> %B, i32 2) + %tmp1 = getelementptr i16* %A, i32 %inc + store i16* %tmp1, i16** %ptr + ret void +} + +define void @test_vst4_fx_update(float** %ptr, <4 x float> %B) nounwind { +; CHECK: test_vst4_fx_update +; CHECK: st4 {v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s}, [{{x[0-9]+|sp}}], #64 + %A = load float** %ptr + %tmp0 = bitcast float* %A to i8* + call void @llvm.arm.neon.vst4.v4f32(i8* %tmp0, <4 x float> %B, <4 x float> %B, <4 x float> %B, <4 x float> %B, i32 4) + %tmp1 = getelementptr float* %A, i32 16 + store float* %tmp1, float** %ptr + ret void +} + +define void @test_vst4_reg_update(i8** %ptr, <8 x i8> %B, i32 %inc) nounwind { +; CHECK: test_vst4_reg_update +; CHECK: st4 {v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b}, [{{x[0-9]+|sp}}], x{{[0-9]+}} + %A = load i8** %ptr + call void @llvm.arm.neon.vst4.v8i8(i8* %A, <8 x i8> %B, <8 x i8> %B, <8 x i8> %B, <8 x i8> %B, i32 1) + %tmp0 = getelementptr i8* %A, i32 %inc + store i8* %tmp0, i8** %ptr + ret void +} + + +declare <4 x i16> @llvm.arm.neon.vld1.v4i16(i8*, i32) +declare <2 x i32> @llvm.arm.neon.vld1.v2i32(i8*, i32) +declare { <16 x i8>, <16 x i8> } @llvm.arm.neon.vld2.v16i8(i8*, i32) +declare { <2 x float>, <2 x float> } @llvm.arm.neon.vld2.v2f32(i8*, i32) +declare { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld3.v4i16(i8*, i32) +declare { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm.neon.vld3.v4i32(i8*, i32) +declare { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld4.v8i16(i8*, i32) +declare { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm.neon.vld4.v8i8(i8*, i32) + +declare void @llvm.arm.neon.vst1.v2f32(i8*, <2 x float>, i32) +declare void @llvm.arm.neon.vst1.v8i16(i8*, <8 x i16>, i32) +declare void @llvm.arm.neon.vst2.v1i64(i8*, <1 x i64>, <1 x i64>, i32) +declare void @llvm.arm.neon.vst2.v8i8(i8*, <8 x i8>, <8 x i8>, i32) +declare void @llvm.arm.neon.vst3.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, i32) +declare void @llvm.arm.neon.vst3.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, i32) +declare void @llvm.arm.neon.vst4.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, <4 x float>, i32) +declare void @llvm.arm.neon.vst4.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, i32) diff --git a/test/MC/AArch64/neon-diagnostics.s b/test/MC/AArch64/neon-diagnostics.s index 4e1207f031..a43287d94b 100644 --- a/test/MC/AArch64/neon-diagnostics.s +++ b/test/MC/AArch64/neon-diagnostics.s @@ -4102,6 +4102,62 @@ // CHECK-ERROR: st4 {v31.2s-v1.2s}, [x31] // CHECK-ERROR: ^ +//---------------------------------------------------------------------- +// Vector post-index load/store multiple N-element structure +// (class SIMD lselem-post) +//---------------------------------------------------------------------- + ld1 {v0.16b}, [x0], #8 + ld1 {v0.8h, v1.16h}, [x0], x1 + ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], #24 +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ld1 {v0.16b}, [x0], #8 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected vector type register +// CHECK-ERROR: ld1 {v0.8h, v1.16h}, [x0], x1 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], #24 +// CHECK-ERROR: ^ + + ld2 {v0.16b, v1.16b}, [x0], #16 + ld3 {v5.2s, v6.2s, v7.2s}, [x1], #48 + ld4 {v31.2d, v0.2d, v1.2d, v2.1d}, [x3], x1 +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ld2 {v0.16b, v1.16b}, [x0], #16 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ld3 {v5.2s, v6.2s, v7.2s}, [x1], #48 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: ld4 {v31.2d, v0.2d, v1.2d, v2.1d}, [x3], x1 +// CHECK-ERROR: ^ + + st1 {v0.16b}, [x0], #8 + st1 {v0.8h, v1.16h}, [x0], x1 + st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], #24 +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: st1 {v0.16b}, [x0], #8 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected vector type register +// CHECK-ERROR: st1 {v0.8h, v1.16h}, [x0], x1 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], #24 + ^ + + st2 {v0.16b, v1.16b}, [x0], #16 + st3 {v5.2s, v6.2s, v7.2s}, [x1], #48 + st4 {v31.2d, v0.2d, v1.2d, v2.1d}, [x3], x1 +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: st2 {v0.16b, v1.16b}, [x0], #16 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: st3 {v5.2s, v6.2s, v7.2s}, [x1], #48 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: st4 {v31.2d, v0.2d, v1.2d, v2.1d}, [x3], x1 +// CHECK-ERROR: ^ + ins v2.b[16], w1 ins v7.h[8], w14 ins v20.s[5], w30 diff --git a/test/MC/AArch64/neon-simd-post-ldst-multi-elem.s b/test/MC/AArch64/neon-simd-post-ldst-multi-elem.s new file mode 100644 index 0000000000..8dc271e38d --- /dev/null +++ b/test/MC/AArch64/neon-simd-post-ldst-multi-elem.s @@ -0,0 +1,389 @@ +// RUN: llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + +//------------------------------------------------------------------------------ +// Load multiple 1-element structures from one register (post-index) +//------------------------------------------------------------------------------ + ld1 {v0.16b}, [x0], x1 + ld1 {v15.8h}, [x15], x2 + ld1 {v31.4s}, [sp], #16 + ld1 {v0.2d}, [x0], #16 + ld1 {v0.8b}, [x0], x2 + ld1 {v15.4h}, [x15], x3 + ld1 {v31.2s}, [sp], #8 + ld1 {v0.1d}, [x0], #8 +// CHECK: ld1 {v0.16b}, [x0], x1 +// CHECK: // encoding: [0x00,0x70,0xc1,0x4c] +// CHECK: ld1 {v15.8h}, [x15], x2 +// CHECK: // encoding: [0xef,0x75,0xc2,0x4c] +// CHECK: ld1 {v31.4s}, [sp], #16 +// CHECK: // encoding: [0xff,0x7b,0xdf,0x4c] +// CHECK: ld1 {v0.2d}, [x0], #16 +// CHECK: // encoding: [0x00,0x7c,0xdf,0x4c] +// CHECK: ld1 {v0.8b}, [x0], x2 +// CHECK: // encoding: [0x00,0x70,0xc2,0x0c] +// CHECK: ld1 {v15.4h}, [x15], x3 +// CHECK: // encoding: [0xef,0x75,0xc3,0x0c] +// CHECK: ld1 {v31.2s}, [sp], #8 +// CHECK: // encoding: [0xff,0x7b,0xdf,0x0c] +// CHECK: ld1 {v0.1d}, [x0], #8 +// CHECK: // encoding: [0x00,0x7c,0xdf,0x0c] + +//------------------------------------------------------------------------------ +// Load multiple 1-element structures from two consecutive registers +// (post-index) +//------------------------------------------------------------------------------ + ld1 {v0.16b, v1.16b}, [x0], x1 + ld1 {v15.8h, v16.8h}, [x15], x2 + ld1 {v31.4s, v0.4s}, [sp], #32 + ld1 {v0.2d, v1.2d}, [x0], #32 + ld1 {v0.8b, v1.8b}, [x0], x2 + ld1 {v15.4h, v16.4h}, [x15], x3 + ld1 {v31.2s, v0.2s}, [sp], #16 + ld1 {v0.1d, v1.1d}, [x0], #16 +// CHECK: ld1 {v0.16b, v1.16b}, [x0], x1 +// CHECK: // encoding: [0x00,0xa0,0xc1,0x4c] +// CHECK: ld1 {v15.8h, v16.8h}, [x15], x2 +// CHECK: // encoding: [0xef,0xa5,0xc2,0x4c] +// CHECK: ld1 {v31.4s, v0.4s}, [sp], #32 +// CHECK: // encoding: [0xff,0xab,0xdf,0x4c] +// CHECK: ld1 {v0.2d, v1.2d}, [x0], #32 +// CHECK: // encoding: [0x00,0xac,0xdf,0x4c] +// CHECK: ld1 {v0.8b, v1.8b}, [x0], x2 +// CHECK: // encoding: [0x00,0xa0,0xc2,0x0c] +// CHECK: ld1 {v15.4h, v16.4h}, [x15], x3 +// CHECK: // encoding: [0xef,0xa5,0xc3,0x0c] +// CHECK: ld1 {v31.2s, v0.2s}, [sp], #16 +// CHECK: // encoding: [0xff,0xab,0xdf,0x0c] +// CHECK: ld1 {v0.1d, v1.1d}, [x0], #16 +// CHECK: // encoding: [0x00,0xac,0xdf,0x0c] + +//------------------------------------------------------------------------------ +// Load multiple 1-element structures from three consecutive registers +// (post-index) +//------------------------------------------------------------------------------ + ld1 {v0.16b, v1.16b, v2.16b}, [x0], x1 + ld1 {v15.8h, v16.8h, v17.8h}, [x15], x2 + ld1 {v31.4s, v0.4s, v1.4s}, [sp], #48 + ld1 {v0.2d, v1.2d, v2.2d}, [x0], #48 + ld1 {v0.8b, v1.8b, v2.8b}, [x0], x2 + ld1 {v15.4h, v16.4h, v17.4h}, [x15], x3 + ld1 {v31.2s, v0.2s, v1.2s}, [sp], #24 + ld1 {v0.1d, v1.1d, v2.1d}, [x0], #24 +// CHECK: ld1 {v0.16b, v1.16b, v2.16b}, [x0], x1 +// CHECK: // encoding: [0x00,0x60,0xc1,0x4c] +// CHECK: ld1 {v15.8h, v16.8h, v17.8h}, [x15], x2 +// CHECK: // encoding: [0xef,0x65,0xc2,0x4c] +// CHECK: ld1 {v31.4s, v0.4s, v1.4s}, [sp], #48 +// CHECK: // encoding: [0xff,0x6b,0xdf,0x4c] +// CHECK: ld1 {v0.2d, v1.2d, v2.2d}, [x0], #48 +// CHECK: // encoding: [0x00,0x6c,0xdf,0x4c] +// CHECK: ld1 {v0.8b, v1.8b, v2.8b}, [x0], x2 +// CHECK: // encoding: [0x00,0x60,0xc2,0x0c] +// CHECK: ld1 {v15.4h, v16.4h, v17.4h}, [x15], x3 +// CHECK: // encoding: [0xef,0x65,0xc3,0x0c] +// CHECK: ld1 {v31.2s, v0.2s, v1.2s}, [sp], #24 +// CHECK: // encoding: [0xff,0x6b,0xdf,0x0c] +// CHECK: ld1 {v0.1d, v1.1d, v2.1d}, [x0], #24 +// CHECK: // encoding: [0x00,0x6c,0xdf,0x0c] + +//------------------------------------------------------------------------------ +// Load multiple 1-element structures from four consecutive registers +// (post-index) +//------------------------------------------------------------------------------ + ld1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1 + ld1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2 + ld1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 + ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64 + ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 + ld1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4 + ld1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32 + ld1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0], #32 +// CHECK: ld1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1 +// CHECK: // encoding: [0x00,0x20,0xc1,0x4c] +// CHECK: ld1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2 +// CHECK: // encoding: [0xef,0x25,0xc2,0x4c] +// CHECK: ld1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 +// CHECK: // encoding: [0xff,0x2b,0xdf,0x4c] +// CHECK: ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64 +// CHECK: // encoding: [0x00,0x2c,0xdf,0x4c] +// CHECK: ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 +// CHECK: // encoding: [0x00,0x20,0xc3,0x0c] +// CHECK: ld1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4 +// CHECK: // encoding: [0xef,0x25,0xc4,0x0c] +// CHECK: ld1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32 +// CHECK: // encoding: [0xff,0x2b,0xdf,0x0c] +// CHECK: ld1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0], #32 +// CHECK: // encoding: [0x00,0x2c,0xdf,0x0c] + +//------------------------------------------------------------------------------ +// Load multiple 2-element structures from two consecutive registers +// (post-index) +//------------------------------------------------------------------------------ + ld2 {v0.16b, v1.16b}, [x0], x1 + ld2 {v15.8h, v16.8h}, [x15], x2 + ld2 {v31.4s, v0.4s}, [sp], #32 + ld2 {v0.2d, v1.2d}, [x0], #32 + ld2 {v0.8b, v1.8b}, [x0], x2 + ld2 {v15.4h, v16.4h}, [x15], x3 + ld2 {v31.2s, v0.2s}, [sp], #16 +// CHECK: ld2 {v0.16b, v1.16b}, [x0], x1 +// CHECK: // encoding: [0x00,0x80,0xc1,0x4c] +// CHECK: ld2 {v15.8h, v16.8h}, [x15], x2 +// CHECK: // encoding: [0xef,0x85,0xc2,0x4c] +// CHECK: ld2 {v31.4s, v0.4s}, [sp], #32 +// CHECK: // encoding: [0xff,0x8b,0xdf,0x4c] +// CHECK: ld2 {v0.2d, v1.2d}, [x0], #32 +// CHECK: // encoding: [0x00,0x8c,0xdf,0x4c] +// CHECK: ld2 {v0.8b, v1.8b}, [x0], x2 +// CHECK: // encoding: [0x00,0x80,0xc2,0x0c] +// CHECK: ld2 {v15.4h, v16.4h}, [x15], x3 +// CHECK: // encoding: [0xef,0x85,0xc3,0x0c] +// CHECK: ld2 {v31.2s, v0.2s}, [sp], #16 +// CHECK: // encoding: [0xff,0x8b,0xdf,0x0c] + +//------------------------------------------------------------------------------ +// Load multiple 3-element structures from three consecutive registers +// (post-index) +//------------------------------------------------------------------------------ + ld3 {v0.16b, v1.16b, v2.16b}, [x0], x1 + ld3 {v15.8h, v16.8h, v17.8h}, [x15], x2 + ld3 {v31.4s, v0.4s, v1.4s}, [sp], #48 + ld3 {v0.2d, v1.2d, v2.2d}, [x0], #48 + ld3 {v0.8b, v1.8b, v2.8b}, [x0], x2 + ld3 {v15.4h, v16.4h, v17.4h}, [x15], x3 + ld3 {v31.2s, v0.2s, v1.2s}, [sp], #24 +// CHECK: ld3 {v0.16b, v1.16b, v2.16b}, [x0], x1 +// CHECK: // encoding: [0x00,0x40,0xc1,0x4c] +// CHECK: ld3 {v15.8h, v16.8h, v17.8h}, [x15], x2 +// CHECK: // encoding: [0xef,0x45,0xc2,0x4c] +// CHECK: ld3 {v31.4s, v0.4s, v1.4s}, [sp], #48 +// CHECK: // encoding: [0xff,0x4b,0xdf,0x4c] +// CHECK: ld3 {v0.2d, v1.2d, v2.2d}, [x0], #48 +// CHECK: // encoding: [0x00,0x4c,0xdf,0x4c] +// CHECK: ld3 {v0.8b, v1.8b, v2.8b}, [x0], x2 +// CHECK: // encoding: [0x00,0x40,0xc2,0x0c] +// CHECK: ld3 {v15.4h, v16.4h, v17.4h}, [x15], x3 +// CHECK: // encoding: [0xef,0x45,0xc3,0x0c] +// CHECK: ld3 {v31.2s, v0.2s, v1.2s}, [sp], #24 +// CHECK: // encoding: [0xff,0x4b,0xdf,0x0c] + +//------------------------------------------------------------------------------ +// Load multiple 4-element structures from four consecutive registers +// (post-index) +//------------------------------------------------------------------------------ + ld4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1 + ld4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2 + ld4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 + ld4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64 + ld4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 + ld4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4 + ld4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32 +// CHECK: ld4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1 +// CHECK: // encoding: [0x00,0x00,0xc1,0x4c] +// CHECK: ld4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2 +// CHECK: // encoding: [0xef,0x05,0xc2,0x4c] +// CHECK: ld4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 +// CHECK: // encoding: [0xff,0x0b,0xdf,0x4c] +// CHECK: ld4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64 +// CHECK: // encoding: [0x00,0x0c,0xdf,0x4c] +// CHECK: ld4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 +// CHECK: // encoding: [0x00,0x00,0xc3,0x0c] +// CHECK: ld4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4 +// CHECK: // encoding: [0xef,0x05,0xc4,0x0c] +// CHECK: ld4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32 +// CHECK: // encoding: [0xff,0x0b,0xdf,0x0c] + +//------------------------------------------------------------------------------ +// Store multiple 1-element structures from one register (post-index) +//------------------------------------------------------------------------------ + st1 {v0.16b}, [x0], x1 + st1 {v15.8h}, [x15], x2 + st1 {v31.4s}, [sp], #16 + st1 {v0.2d}, [x0], #16 + st1 {v0.8b}, [x0], x2 + st1 {v15.4h}, [x15], x3 + st1 {v31.2s}, [sp], #8 + st1 {v0.1d}, [x0], #8 +// CHECK: st1 {v0.16b}, [x0], x1 +// CHECK: // encoding: [0x00,0x70,0x81,0x4c] +// CHECK: st1 {v15.8h}, [x15], x2 +// CHECK: // encoding: [0xef,0x75,0x82,0x4c] +// CHECK: st1 {v31.4s}, [sp], #16 +// CHECK: // encoding: [0xff,0x7b,0x9f,0x4c] +// CHECK: st1 {v0.2d}, [x0], #16 +// CHECK: // encoding: [0x00,0x7c,0x9f,0x4c] +// CHECK: st1 {v0.8b}, [x0], x2 +// CHECK: // encoding: [0x00,0x70,0x82,0x0c] +// CHECK: st1 {v15.4h}, [x15], x3 +// CHECK: // encoding: [0xef,0x75,0x83,0x0c] +// CHECK: st1 {v31.2s}, [sp], #8 +// CHECK: // encoding: [0xff,0x7b,0x9f,0x0c] +// CHECK: st1 {v0.1d}, [x0], #8 +// CHECK: // encoding: [0x00,0x7c,0x9f,0x0c] + +//------------------------------------------------------------------------------ +// Store multiple 1-element structures from two consecutive registers +// (post-index) +//------------------------------------------------------------------------------ + st1 {v0.16b, v1.16b}, [x0], x1 + st1 {v15.8h, v16.8h}, [x15], x2 + st1 {v31.4s, v0.4s}, [sp], #32 + st1 {v0.2d, v1.2d}, [x0], #32 + st1 {v0.8b, v1.8b}, [x0], x2 + st1 {v15.4h, v16.4h}, [x15], x3 + st1 {v31.2s, v0.2s}, [sp], #16 + st1 {v0.1d, v1.1d}, [x0], #16 +// CHECK: st1 {v0.16b, v1.16b}, [x0], x1 +// CHECK: // encoding: [0x00,0xa0,0x81,0x4c] +// CHECK: st1 {v15.8h, v16.8h}, [x15], x2 +// CHECK: // encoding: [0xef,0xa5,0x82,0x4c] +// CHECK: st1 {v31.4s, v0.4s}, [sp], #32 +// CHECK: // encoding: [0xff,0xab,0x9f,0x4c] +// CHECK: st1 {v0.2d, v1.2d}, [x0], #32 +// CHECK: // encoding: [0x00,0xac,0x9f,0x4c] +// CHECK: st1 {v0.8b, v1.8b}, [x0], x2 +// CHECK: // encoding: [0x00,0xa0,0x82,0x0c] +// CHECK: st1 {v15.4h, v16.4h}, [x15], x3 +// CHECK: // encoding: [0xef,0xa5,0x83,0x0c] +// CHECK: st1 {v31.2s, v0.2s}, [sp], #16 +// CHECK: // encoding: [0xff,0xab,0x9f,0x0c] +// CHECK: st1 {v0.1d, v1.1d}, [x0], #16 +// CHECK: // encoding: [0x00,0xac,0x9f,0x0c] + +//------------------------------------------------------------------------------ +// Store multiple 1-element structures from three consecutive registers +// (post-index) +//------------------------------------------------------------------------------ + st1 {v0.16b, v1.16b, v2.16b}, [x0], x1 + st1 {v15.8h, v16.8h, v17.8h}, [x15], x2 + st1 {v31.4s, v0.4s, v1.4s}, [sp], #48 + st1 {v0.2d, v1.2d, v2.2d}, [x0], #48 + st1 {v0.8b, v1.8b, v2.8b}, [x0], x2 + st1 {v15.4h, v16.4h, v17.4h}, [x15], x3 + st1 {v31.2s, v0.2s, v1.2s}, [sp], #24 + st1 {v0.1d, v1.1d, v2.1d}, [x0], #24 +// CHECK: st1 {v0.16b, v1.16b, v2.16b}, [x0], x1 +// CHECK: // encoding: [0x00,0x60,0x81,0x4c] +// CHECK: st1 {v15.8h, v16.8h, v17.8h}, [x15], x2 +// CHECK: // encoding: [0xef,0x65,0x82,0x4c] +// CHECK: st1 {v31.4s, v0.4s, v1.4s}, [sp], #48 +// CHECK: // encoding: [0xff,0x6b,0x9f,0x4c] +// CHECK: st1 {v0.2d, v1.2d, v2.2d}, [x0], #48 +// CHECK: // encoding: [0x00,0x6c,0x9f,0x4c] +// CHECK: st1 {v0.8b, v1.8b, v2.8b}, [x0], x2 +// CHECK: // encoding: [0x00,0x60,0x82,0x0c] +// CHECK: st1 {v15.4h, v16.4h, v17.4h}, [x15], x3 +// CHECK: // encoding: [0xef,0x65,0x83,0x0c] +// CHECK: st1 {v31.2s, v0.2s, v1.2s}, [sp], #24 +// CHECK: // encoding: [0xff,0x6b,0x9f,0x0c] +// CHECK: st1 {v0.1d, v1.1d, v2.1d}, [x0], #24 +// CHECK: // encoding: [0x00,0x6c,0x9f,0x0c] + +//------------------------------------------------------------------------------ +// Store multiple 1-element structures from four consecutive registers +// (post-index) +//------------------------------------------------------------------------------ + st1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1 + st1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2 + st1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 + st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64 + st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 + st1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4 + st1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32 + st1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0], #32 +// CHECK: st1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1 +// CHECK: // encoding: [0x00,0x20,0x81,0x4c] +// CHECK: st1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2 +// CHECK: // encoding: [0xef,0x25,0x82,0x4c] +// CHECK: st1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 +// CHECK: // encoding: [0xff,0x2b,0x9f,0x4c] +// CHECK: st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64 +// CHECK: // encoding: [0x00,0x2c,0x9f,0x4c] +// CHECK: st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 +// CHECK: // encoding: [0x00,0x20,0x83,0x0c] +// CHECK: st1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4 +// CHECK: // encoding: [0xef,0x25,0x84,0x0c] +// CHECK: st1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32 +// CHECK: // encoding: [0xff,0x2b,0x9f,0x0c] +// CHECK: st1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0], #32 +// CHECK: // encoding: [0x00,0x2c,0x9f,0x0c] + +//------------------------------------------------------------------------------ +// Store multiple 2-element structures from two consecutive registers +// (post-index) +//------------------------------------------------------------------------------ + st2 {v0.16b, v1.16b}, [x0], x1 + st2 {v15.8h, v16.8h}, [x15], x2 + st2 {v31.4s, v0.4s}, [sp], #32 + st2 {v0.2d, v1.2d}, [x0], #32 + st2 {v0.8b, v1.8b}, [x0], x2 + st2 {v15.4h, v16.4h}, [x15], x3 + st2 {v31.2s, v0.2s}, [sp], #16 +// CHECK: st2 {v0.16b, v1.16b}, [x0], x1 +// CHECK: // encoding: [0x00,0x80,0x81,0x4c] +// CHECK: st2 {v15.8h, v16.8h}, [x15], x2 +// CHECK: // encoding: [0xef,0x85,0x82,0x4c] +// CHECK: st2 {v31.4s, v0.4s}, [sp], #32 +// CHECK: // encoding: [0xff,0x8b,0x9f,0x4c] +// CHECK: st2 {v0.2d, v1.2d}, [x0], #32 +// CHECK: // encoding: [0x00,0x8c,0x9f,0x4c] +// CHECK: st2 {v0.8b, v1.8b}, [x0], x2 +// CHECK: // encoding: [0x00,0x80,0x82,0x0c] +// CHECK: st2 {v15.4h, v16.4h}, [x15], x3 +// CHECK: // encoding: [0xef,0x85,0x83,0x0c] +// CHECK: st2 {v31.2s, v0.2s}, [sp], #16 +// CHECK: // encoding: [0xff,0x8b,0x9f,0x0c] + +//------------------------------------------------------------------------------ +// Store multiple 3-element structures from three consecutive registers +// (post-index) +//------------------------------------------------------------------------------ + st3 {v0.16b, v1.16b, v2.16b}, [x0], x1 + st3 {v15.8h, v16.8h, v17.8h}, [x15], x2 + st3 {v31.4s, v0.4s, v1.4s}, [sp], #48 + st3 {v0.2d, v1.2d, v2.2d}, [x0], #48 + st3 {v0.8b, v1.8b, v2.8b}, [x0], x2 + st3 {v15.4h, v16.4h, v17.4h}, [x15], x3 + st3 {v31.2s, v0.2s, v1.2s}, [sp], #24 +// CHECK: st3 {v0.16b, v1.16b, v2.16b}, [x0], x1 +// CHECK: // encoding: [0x00,0x40,0x81,0x4c] +// CHECK: st3 {v15.8h, v16.8h, v17.8h}, [x15], x2 +// CHECK: // encoding: [0xef,0x45,0x82,0x4c] +// CHECK: st3 {v31.4s, v0.4s, v1.4s}, [sp], #48 +// CHECK: // encoding: [0xff,0x4b,0x9f,0x4c] +// CHECK: st3 {v0.2d, v1.2d, v2.2d}, [x0], #48 +// CHECK: // encoding: [0x00,0x4c,0x9f,0x4c] +// CHECK: st3 {v0.8b, v1.8b, v2.8b}, [x0], x2 +// CHECK: // encoding: [0x00,0x40,0x82,0x0c] +// CHECK: st3 {v15.4h, v16.4h, v17.4h}, [x15], x3 +// CHECK: // encoding: [0xef,0x45,0x83,0x0c] +// CHECK: st3 {v31.2s, v0.2s, v1.2s}, [sp], #24 +// CHECK: // encoding: [0xff,0x4b,0x9f,0x0c] + +//------------------------------------------------------------------------------ +// Store multiple 4-element structures from four consecutive registers +// (post-index) +//------------------------------------------------------------------------------ + st4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1 + st4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2 + st4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 + st4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64 + st4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 + st4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4 + st4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32 +// CHECK: st4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1 +// CHECK: // encoding: [0x00,0x00,0x81,0x4c] +// CHECK: st4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2 +// CHECK: // encoding: [0xef,0x05,0x82,0x4c] +// CHECK: st4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 +// CHECK: // encoding: [0xff,0x0b,0x9f,0x4c] +// CHECK: st4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64 +// CHECK: // encoding: [0x00,0x0c,0x9f,0x4c] +// CHECK: st4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 +// CHECK: // encoding: [0x00,0x00,0x83,0x0c] +// CHECK: st4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4 +// CHECK: // encoding: [0xef,0x05,0x84,0x0c] +// CHECK: st4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32 +// CHECK: // encoding: [0xff,0x0b,0x9f,0x0c] diff --git a/test/MC/Disassembler/AArch64/neon-instructions.txt b/test/MC/Disassembler/AArch64/neon-instructions.txt index e97728283b..c320d7da09 100644 --- a/test/MC/Disassembler/AArch64/neon-instructions.txt +++ b/test/MC/Disassembler/AArch64/neon-instructions.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -disassemble < %s | FileCheck %s +G# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -disassemble < %s | FileCheck %s #------------------------------------------------------------------------------ # Vector Integer Add/Sub @@ -1971,3 +1971,74 @@ # CHECK: ucvtf d21, d14, #64 0xb6,0xe5,0x20,0x7f 0xd5,0xe5,0x40,0x7f + +#---------------------------------------------------------------------- +# Vector load/store multiple N-element structure +#---------------------------------------------------------------------- +# CHECK: ld1 {v0.16b}, [x0] +# CHECK: ld1 {v15.8h, v16.8h}, [x15] +# CHECK: ld1 {v31.4s, v0.4s, v1.4s}, [sp] +# CHECK: ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] +0x00,0x70,0x40,0x4c +0xef,0xa5,0x40,0x4c +0xff,0x6b,0x40,0x4c +0x00,0x2c,0x40,0x4c + +# CHECK: ld2 {v0.8b, v1.8b}, [x0] +# CHECK: ld3 {v15.4h, v16.4h, v17.4h}, [x15] +# CHECK: ld4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] +0x00,0x80,0x40,0x0c +0xef,0x45,0x40,0x0c +0xff,0x0b,0x40,0x0c + +# CHECK: st1 {v0.16b}, [x0] +# CHECK: st1 {v15.8h, v16.8h}, [x15] +# CHECK: st1 {v31.4s, v0.4s, v1.4s}, [sp] +# CHECK: st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] +0x00,0x70,0x00,0x4c +0xef,0xa5,0x00,0x4c +0xff,0x6b,0x00,0x4c +0x00,0x2c,0x00,0x4c + +# CHECK: st2 {v0.8b, v1.8b}, [x0] +# CHECK: st3 {v15.4h, v16.4h, v17.4h}, [x15] +# CHECK: st4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] +0x00,0x80,0x00,0x0c +0xef,0x45,0x00,0x0c +0xff,0x0b,0x00,0x0c + +#---------------------------------------------------------------------- +# Vector load/store multiple N-element structure (post-index) +#---------------------------------------------------------------------- +# CHECK: ld1 {v15.8h}, [x15], x2 +# CHECK: ld1 {v31.4s, v0.4s}, [sp], #32 +# CHECK: ld1 {v0.2d, v1.2d, v2.2d}, [x0], #48 +# CHECK: ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 +0xef,0x75,0xc2,0x4c +0xff,0xab,0xdf,0x4c +0x00,0x6c,0xdf,0x4c +0x00,0x20,0xc3,0x0c + +# CHECK: ld2 {v0.16b, v1.16b}, [x0], x1 +# CHECK: ld3 {v15.8h, v16.8h, v17.8h}, [x15], x2 +# CHECK: ld4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 +0x00,0x80,0xc1,0x4c +0xef,0x45,0xc2,0x4c +0xff,0x0b,0xdf,0x4c + + +# CHECK: st1 {v15.8h}, [x15], x2 +# CHECK: st1 {v31.4s, v0.4s}, [sp], #32 +# CHECK: st1 {v0.2d, v1.2d, v2.2d}, [x0], #48 +# CHECK: st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 +0xef,0x75,0x82,0x4c +0xff,0xab,0x9f,0x4c +0x00,0x6c,0x9f,0x4c +0x00,0x20,0x83,0x0c + +# CHECK: st2 {v0.16b, v1.16b}, [x0], x1 +# CHECK: st3 {v15.8h, v16.8h, v17.8h}, [x15], x2 +# CHECK: st4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 +0x00,0x80,0x81,0x4c +0xef,0x45,0x82,0x4c +0xff,0x0b,0x9f,0x4c -- cgit v1.2.3