From 8d9550bde95c8d128e7bf62e9e65dec1854e2d1d Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Thu, 22 Dec 2011 18:04:04 +0000 Subject: ARM assembler should accept shift-by-zero for any shifted-immediate operand. Just treat it as-if the shift wasn't there at all. 'as' compatibility. rdar://10604767 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147153 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/MC/ARM/arm-aliases.s | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 test/MC/ARM/arm-aliases.s (limited to 'test') diff --git a/test/MC/ARM/arm-aliases.s b/test/MC/ARM/arm-aliases.s new file mode 100644 index 0000000000..d4ea0dfcb5 --- /dev/null +++ b/test/MC/ARM/arm-aliases.s @@ -0,0 +1,17 @@ +@ RUN: llvm-mc -triple=armv7-apple-darwin -show-encoding < %s | FileCheck %s + .syntax unified + +@ Shift-by-zero should canonicalize to no shift at all (lsl #0 encoding) + add r1, r2, r3, lsl #0 + sub r1, r2, r3, ror #0 + eor r1, r2, r3, lsr #0 + orr r1, r2, r3, asr #0 + and r1, r2, r3, ror #0 + bic r1, r2, r3, lsl #0 + +@ CHECK: add r1, r2, r3 @ encoding: [0x03,0x10,0x82,0xe0] +@ CHECK: sub r1, r2, r3 @ encoding: [0x03,0x10,0x42,0xe0] +@ CHECK: eor r1, r2, r3 @ encoding: [0x03,0x10,0x22,0xe0] +@ CHECK: orr r1, r2, r3 @ encoding: [0x03,0x10,0x82,0xe1] +@ CHECK: and r1, r2, r3 @ encoding: [0x03,0x10,0x02,0xe0] +@ CHECK: bic r1, r2, r3 @ encoding: [0x03,0x10,0xc2,0xe1] -- cgit v1.2.3