From 9eefea009fb559cf441254f7022a2824386852c6 Mon Sep 17 00:00:00 2001 From: Amaury de la Vieuville Date: Sat, 8 Jun 2013 13:54:05 +0000 Subject: ARM: fix VMOVvnf32 decoding when ambiguous with VCVT Enforce Table A7-15 (op=1, cmode=0b111) -> UNDEF git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183612 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/MC/Disassembler/ARM/invalid-VMOV-arm.txt | 7 +++++++ 1 file changed, 7 insertions(+) create mode 100644 test/MC/Disassembler/ARM/invalid-VMOV-arm.txt (limited to 'test') diff --git a/test/MC/Disassembler/ARM/invalid-VMOV-arm.txt b/test/MC/Disassembler/ARM/invalid-VMOV-arm.txt new file mode 100644 index 0000000000..9d6cd5cb3b --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-VMOV-arm.txt @@ -0,0 +1,7 @@ +# VMOV cmode=0b1111 op=1 +# RUN: echo "0x70 0xef 0xc7 0xf3" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s + +# VMOV cmode=0b1111 op=1 +# RUN: echo "0x30 0x0f 0x80 0xf3" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s + +# CHECK: invalid instruction encoding -- cgit v1.2.3