From a08063a000cfc7499f08a472d85f14e7a5e90f8d Mon Sep 17 00:00:00 2001 From: Kevin Qin Date: Thu, 14 Nov 2013 02:44:13 +0000 Subject: Implement aarch64 neon instruction class SIMD misc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194656 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/AArch64/neon-compare-instructions.ll | 168 ++-- test/MC/AArch64/neon-diagnostics.s | 1034 +++++++++++++++++++++ 2 files changed, 1090 insertions(+), 112 deletions(-) (limited to 'test') diff --git a/test/CodeGen/AArch64/neon-compare-instructions.ll b/test/CodeGen/AArch64/neon-compare-instructions.ll index 0848f9b03d..68f03425b2 100644 --- a/test/CodeGen/AArch64/neon-compare-instructions.ll +++ b/test/CodeGen/AArch64/neon-compare-instructions.ll @@ -51,8 +51,7 @@ define <2 x i64> @cmeq2xi64(<2 x i64> %A, <2 x i64> %B) { define <8 x i8> @cmne8xi8(<8 x i8> %A, <8 x i8> %B) { ;CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b -;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b %tmp3 = icmp ne <8 x i8> %A, %B; %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> ret <8 x i8> %tmp4 @@ -60,8 +59,7 @@ define <8 x i8> @cmne8xi8(<8 x i8> %A, <8 x i8> %B) { define <16 x i8> @cmne16xi8(<16 x i8> %A, <16 x i8> %B) { ;CHECK: cmeq {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = icmp ne <16 x i8> %A, %B; %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> ret <16 x i8> %tmp4 @@ -69,8 +67,7 @@ define <16 x i8> @cmne16xi8(<16 x i8> %A, <16 x i8> %B) { define <4 x i16> @cmne4xi16(<4 x i16> %A, <4 x i16> %B) { ;CHECK: cmeq {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h -;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b %tmp3 = icmp ne <4 x i16> %A, %B; %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> ret <4 x i16> %tmp4 @@ -78,8 +75,7 @@ define <4 x i16> @cmne4xi16(<4 x i16> %A, <4 x i16> %B) { define <8 x i16> @cmne8xi16(<8 x i16> %A, <8 x i16> %B) { ;CHECK: cmeq {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = icmp ne <8 x i16> %A, %B; %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> ret <8 x i16> %tmp4 @@ -87,8 +83,7 @@ define <8 x i16> @cmne8xi16(<8 x i16> %A, <8 x i16> %B) { define <2 x i32> @cmne2xi32(<2 x i32> %A, <2 x i32> %B) { ;CHECK: cmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s -;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b %tmp3 = icmp ne <2 x i32> %A, %B; %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -96,8 +91,7 @@ define <2 x i32> @cmne2xi32(<2 x i32> %A, <2 x i32> %B) { define <4 x i32> @cmne4xi32(<4 x i32> %A, <4 x i32> %B) { ;CHECK: cmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = icmp ne <4 x i32> %A, %B; %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 @@ -105,8 +99,7 @@ define <4 x i32> @cmne4xi32(<4 x i32> %A, <4 x i32> %B) { define <2 x i64> @cmne2xi64(<2 x i64> %A, <2 x i64> %B) { ;CHECK: cmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = icmp ne <2 x i64> %A, %B; %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> ret <2 x i64> %tmp4 @@ -867,8 +860,7 @@ define <2 x i64> @cmltz2xi64(<2 x i64> %A) { define <8 x i8> @cmneqz8xi8(<8 x i8> %A) { ;CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0x0 -;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b %tmp3 = icmp ne <8 x i8> %A, zeroinitializer; %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> ret <8 x i8> %tmp4 @@ -876,8 +868,7 @@ define <8 x i8> @cmneqz8xi8(<8 x i8> %A) { define <16 x i8> @cmneqz16xi8(<16 x i8> %A) { ;CHECK: cmeq {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #0x0 -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = icmp ne <16 x i8> %A, zeroinitializer; %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> ret <16 x i8> %tmp4 @@ -885,8 +876,7 @@ define <16 x i8> @cmneqz16xi8(<16 x i8> %A) { define <4 x i16> @cmneqz4xi16(<4 x i16> %A) { ;CHECK: cmeq {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #0x0 -;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b %tmp3 = icmp ne <4 x i16> %A, zeroinitializer; %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> ret <4 x i16> %tmp4 @@ -894,8 +884,7 @@ define <4 x i16> @cmneqz4xi16(<4 x i16> %A) { define <8 x i16> @cmneqz8xi16(<8 x i16> %A) { ;CHECK: cmeq {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #0x0 -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = icmp ne <8 x i16> %A, zeroinitializer; %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> ret <8 x i16> %tmp4 @@ -903,8 +892,7 @@ define <8 x i16> @cmneqz8xi16(<8 x i16> %A) { define <2 x i32> @cmneqz2xi32(<2 x i32> %A) { ;CHECK: cmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0x0 -;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b %tmp3 = icmp ne <2 x i32> %A, zeroinitializer; %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -912,8 +900,7 @@ define <2 x i32> @cmneqz2xi32(<2 x i32> %A) { define <4 x i32> @cmneqz4xi32(<4 x i32> %A) { ;CHECK: cmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0x0 -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = icmp ne <4 x i32> %A, zeroinitializer; %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 @@ -921,8 +908,7 @@ define <4 x i32> @cmneqz4xi32(<4 x i32> %A) { define <2 x i64> @cmneqz2xi64(<2 x i64> %A) { ;CHECK: cmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0x0 -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = icmp ne <2 x i64> %A, zeroinitializer; %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> ret <2 x i64> %tmp4 @@ -1369,8 +1355,7 @@ define <2 x i32> @fcmuno2xfloat(<2 x float> %A, <2 x float> %B) { ;CHECK: fcmge {{v[0-9]+}}.2s, v0.2s, v1.2s ;CHECK-NEXT: fcmgt {{v[0-9]+}}.2s, v1.2s, v0.2s ;CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b -;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b %tmp3 = fcmp uno <2 x float> %A, %B %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -1382,8 +1367,7 @@ define <4 x i32> @fcmuno4xfloat(<4 x float> %A, <4 x float> %B) { ;CHECK: fcmge {{v[0-9]+}}.4s, v0.4s, v1.4s ;CHECK-NEXT: fcmgt {{v[0-9]+}}.4s, v1.4s, v0.4s ;CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp uno <4 x float> %A, %B %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 @@ -1395,8 +1379,7 @@ define <2 x i64> @fcmuno2xdouble(<2 x double> %A, <2 x double> %B) { ;CHECK: fcmge {{v[0-9]+}}.2d, v0.2d, v1.2d ;CHECK-NEXT: fcmgt {{v[0-9]+}}.2d, v1.2d, v0.2d ;CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp uno <2 x double> %A, %B %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> ret <2 x i64> %tmp4 @@ -1408,8 +1391,7 @@ define <2 x i32> @fcmueq2xfloat(<2 x float> %A, <2 x float> %B) { ;CHECK: fcmgt {{v[0-9]+}}.2s, v0.2s, v1.2s ;CHECK-NEXT: fcmgt {{v[0-9]+}}.2s, v1.2s, v0.2s ;CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b -;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b %tmp3 = fcmp ueq <2 x float> %A, %B %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -1421,8 +1403,7 @@ define <4 x i32> @fcmueq4xfloat(<4 x float> %A, <4 x float> %B) { ;CHECK: fcmgt {{v[0-9]+}}.4s, v0.4s, v1.4s ;CHECK-NEXT: fcmgt {{v[0-9]+}}.4s, v1.4s, v0.4s ;CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp ueq <4 x float> %A, %B %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 @@ -1434,8 +1415,7 @@ define <2 x i64> @fcmueq2xdouble(<2 x double> %A, <2 x double> %B) { ;CHECK: fcmgt {{v[0-9]+}}.2d, v0.2d, v1.2d ;CHECK-NEXT: fcmgt {{v[0-9]+}}.2d, v1.2d, v0.2d ;CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp ueq <2 x double> %A, %B %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> ret <2 x i64> %tmp4 @@ -1445,8 +1425,7 @@ define <2 x i32> @fcmuge2xfloat(<2 x float> %A, <2 x float> %B) { ; Using registers other than v0, v1 are possible, but would be odd. ; UGE = ULE with swapped operands, ULE implemented as !OGT. ;CHECK: fcmgt {{v[0-9]+}}.2s, v1.2s, v0.2s -;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b %tmp3 = fcmp uge <2 x float> %A, %B %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -1456,8 +1435,7 @@ define <4 x i32> @fcmuge4xfloat(<4 x float> %A, <4 x float> %B) { ; Using registers other than v0, v1 are possible, but would be odd. ; UGE = ULE with swapped operands, ULE implemented as !OGT. ;CHECK: fcmgt {{v[0-9]+}}.4s, v1.4s, v0.4s -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp uge <4 x float> %A, %B %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 @@ -1467,8 +1445,7 @@ define <2 x i64> @fcmuge2xdouble(<2 x double> %A, <2 x double> %B) { ; Using registers other than v0, v1 are possible, but would be odd. ; UGE = ULE with swapped operands, ULE implemented as !OGT. ;CHECK: fcmgt {{v[0-9]+}}.2d, v1.2d, v0.2d -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp uge <2 x double> %A, %B %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> ret <2 x i64> %tmp4 @@ -1478,8 +1455,7 @@ define <2 x i32> @fcmugt2xfloat(<2 x float> %A, <2 x float> %B) { ; Using registers other than v0, v1 are possible, but would be odd. ; UGT = ULT with swapped operands, ULT implemented as !OGE. ;CHECK: fcmge {{v[0-9]+}}.2s, v1.2s, v0.2s -;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b %tmp3 = fcmp ugt <2 x float> %A, %B %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -1489,16 +1465,14 @@ define <4 x i32> @fcmugt4xfloat(<4 x float> %A, <4 x float> %B) { ; Using registers other than v0, v1 are possible, but would be odd. ; UGT = ULT with swapped operands, ULT implemented as !OGE. ;CHECK: fcmge {{v[0-9]+}}.4s, v1.4s, v0.4s -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp ugt <4 x float> %A, %B %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 } define <2 x i64> @fcmugt2xdouble(<2 x double> %A, <2 x double> %B) { ;CHECK: fcmge {{v[0-9]+}}.2d, v1.2d, v0.2d -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp ugt <2 x double> %A, %B %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> ret <2 x i64> %tmp4 @@ -1508,8 +1482,7 @@ define <2 x i32> @fcmule2xfloat(<2 x float> %A, <2 x float> %B) { ; Using registers other than v0, v1 are possible, but would be odd. ; ULE implemented as !OGT. ;CHECK: fcmgt {{v[0-9]+}}.2s, v0.2s, v1.2s -;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b %tmp3 = fcmp ule <2 x float> %A, %B %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -1519,8 +1492,7 @@ define <4 x i32> @fcmule4xfloat(<4 x float> %A, <4 x float> %B) { ; Using registers other than v0, v1 are possible, but would be odd. ; ULE implemented as !OGT. ;CHECK: fcmgt {{v[0-9]+}}.4s, v0.4s, v1.4s -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp ule <4 x float> %A, %B %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 @@ -1529,8 +1501,7 @@ define <2 x i64> @fcmule2xdouble(<2 x double> %A, <2 x double> %B) { ; Using registers other than v0, v1 are possible, but would be odd. ; ULE implemented as !OGT. ;CHECK: fcmgt {{v[0-9]+}}.2d, v0.2d, v1.2d -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp ule <2 x double> %A, %B %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> ret <2 x i64> %tmp4 @@ -1540,8 +1511,7 @@ define <2 x i32> @fcmult2xfloat(<2 x float> %A, <2 x float> %B) { ; Using registers other than v0, v1 are possible, but would be odd. ; ULT implemented as !OGE. ;CHECK: fcmge {{v[0-9]+}}.2s, v0.2s, v1.2s -;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b %tmp3 = fcmp ult <2 x float> %A, %B %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -1551,8 +1521,7 @@ define <4 x i32> @fcmult4xfloat(<4 x float> %A, <4 x float> %B) { ; Using registers other than v0, v1 are possible, but would be odd. ; ULT implemented as !OGE. ;CHECK: fcmge {{v[0-9]+}}.4s, v0.4s, v1.4s -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp ult <4 x float> %A, %B %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 @@ -1561,8 +1530,7 @@ define <2 x i64> @fcmult2xdouble(<2 x double> %A, <2 x double> %B) { ; Using registers other than v0, v1 are possible, but would be odd. ; ULT implemented as !OGE. ;CHECK: fcmge {{v[0-9]+}}.2d, v0.2d, v1.2d -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp ult <2 x double> %A, %B %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> ret <2 x i64> %tmp4 @@ -1572,8 +1540,7 @@ define <2 x i32> @fcmune2xfloat(<2 x float> %A, <2 x float> %B) { ; Using registers other than v0, v1 are possible, but would be odd. ; UNE = !OEQ. ;CHECK: fcmeq {{v[0-9]+}}.2s, v0.2s, v1.2s -;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b %tmp3 = fcmp une <2 x float> %A, %B %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -1583,8 +1550,7 @@ define <4 x i32> @fcmune4xfloat(<4 x float> %A, <4 x float> %B) { ; Using registers other than v0, v1 are possible, but would be odd. ; UNE = !OEQ. ;CHECK: fcmeq {{v[0-9]+}}.4s, v0.4s, v1.4s -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp une <4 x float> %A, %B %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 @@ -1593,8 +1559,7 @@ define <2 x i64> @fcmune2xdouble(<2 x double> %A, <2 x double> %B) { ; Using registers other than v0, v1 are possible, but would be odd. ; UNE = !OEQ. ;CHECK: fcmeq {{v[0-9]+}}.2d, v0.2d, v1.2d -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp une <2 x double> %A, %B %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> ret <2 x i64> %tmp4 @@ -1766,8 +1731,7 @@ define <2 x i32> @fcmueqz2xfloat(<2 x float> %A) { ;CHECK: fcmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0.0 ;CHECK-NEXT: fcmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0.0 ;CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b -;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b %tmp3 = fcmp ueq <2 x float> %A, zeroinitializer %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -1778,8 +1742,7 @@ define <4 x i32> @fcmueqz4xfloat(<4 x float> %A) { ;CHECK: fcmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0.0 ;CHECK-NEXT: fcmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0.0 ;CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp ueq <4 x float> %A, zeroinitializer %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 @@ -1790,8 +1753,7 @@ define <2 x i64> @fcmueqz2xdouble(<2 x double> %A) { ;CHECK: fcmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0.0 ;CHECK-NEXT: fcmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0.0 ;CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp ueq <2 x double> %A, zeroinitializer %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> ret <2 x i64> %tmp4 @@ -1800,8 +1762,7 @@ define <2 x i64> @fcmueqz2xdouble(<2 x double> %A) { define <2 x i32> @fcmugez2xfloat(<2 x float> %A) { ; UGE with zero = !OLT ;CHECK: fcmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0.0 -;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b %tmp3 = fcmp uge <2 x float> %A, zeroinitializer %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -1810,8 +1771,7 @@ define <2 x i32> @fcmugez2xfloat(<2 x float> %A) { define <4 x i32> @fcmugez4xfloat(<4 x float> %A) { ; UGE with zero = !OLT ;CHECK: fcmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0.0 -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp uge <4 x float> %A, zeroinitializer %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 @@ -1819,8 +1779,7 @@ define <4 x i32> @fcmugez4xfloat(<4 x float> %A) { define <2 x i64> @fcmugez2xdouble(<2 x double> %A) { ; UGE with zero = !OLT ;CHECK: fcmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0.0 -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp uge <2 x double> %A, zeroinitializer %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> ret <2 x i64> %tmp4 @@ -1829,8 +1788,7 @@ define <2 x i64> @fcmugez2xdouble(<2 x double> %A) { define <2 x i32> @fcmugtz2xfloat(<2 x float> %A) { ; UGT with zero = !OLE ;CHECK: fcmle {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0.0 -;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b %tmp3 = fcmp ugt <2 x float> %A, zeroinitializer %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -1839,8 +1797,7 @@ define <2 x i32> @fcmugtz2xfloat(<2 x float> %A) { define <4 x i32> @fcmugtz4xfloat(<4 x float> %A) { ; UGT with zero = !OLE ;CHECK: fcmle {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0.0 -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp ugt <4 x float> %A, zeroinitializer %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 @@ -1848,8 +1805,7 @@ define <4 x i32> @fcmugtz4xfloat(<4 x float> %A) { define <2 x i64> @fcmugtz2xdouble(<2 x double> %A) { ; UGT with zero = !OLE ;CHECK: fcmle {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0.0 -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp ugt <2 x double> %A, zeroinitializer %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> ret <2 x i64> %tmp4 @@ -1858,8 +1814,7 @@ define <2 x i64> @fcmugtz2xdouble(<2 x double> %A) { define <2 x i32> @fcmultz2xfloat(<2 x float> %A) { ; ULT with zero = !OGE ;CHECK: fcmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0.0 -;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b %tmp3 = fcmp ult <2 x float> %A, zeroinitializer %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -1867,8 +1822,7 @@ define <2 x i32> @fcmultz2xfloat(<2 x float> %A) { define <4 x i32> @fcmultz4xfloat(<4 x float> %A) { ;CHECK: fcmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0.0 -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp ult <4 x float> %A, zeroinitializer %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 @@ -1876,8 +1830,7 @@ define <4 x i32> @fcmultz4xfloat(<4 x float> %A) { define <2 x i64> @fcmultz2xdouble(<2 x double> %A) { ;CHECK: fcmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0.0 -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp ult <2 x double> %A, zeroinitializer %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> ret <2 x i64> %tmp4 @@ -1887,8 +1840,7 @@ define <2 x i64> @fcmultz2xdouble(<2 x double> %A) { define <2 x i32> @fcmulez2xfloat(<2 x float> %A) { ; ULE with zero = !OGT ;CHECK: fcmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0.0 -;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b %tmp3 = fcmp ule <2 x float> %A, zeroinitializer %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -1897,8 +1849,7 @@ define <2 x i32> @fcmulez2xfloat(<2 x float> %A) { define <4 x i32> @fcmulez4xfloat(<4 x float> %A) { ; ULE with zero = !OGT ;CHECK: fcmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0.0 -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp ule <4 x float> %A, zeroinitializer %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 @@ -1907,8 +1858,7 @@ define <4 x i32> @fcmulez4xfloat(<4 x float> %A) { define <2 x i64> @fcmulez2xdouble(<2 x double> %A) { ; ULE with zero = !OGT ;CHECK: fcmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0.0 -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp ule <2 x double> %A, zeroinitializer %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> ret <2 x i64> %tmp4 @@ -1917,8 +1867,7 @@ define <2 x i64> @fcmulez2xdouble(<2 x double> %A) { define <2 x i32> @fcmunez2xfloat(<2 x float> %A) { ; UNE with zero = !OEQ with zero ;CHECK: fcmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0.0 -;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b %tmp3 = fcmp une <2 x float> %A, zeroinitializer %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -1927,8 +1876,7 @@ define <2 x i32> @fcmunez2xfloat(<2 x float> %A) { define <4 x i32> @fcmunez4xfloat(<4 x float> %A) { ; UNE with zero = !OEQ with zero ;CHECK: fcmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0.0 -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp une <4 x float> %A, zeroinitializer %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 @@ -1936,8 +1884,7 @@ define <4 x i32> @fcmunez4xfloat(<4 x float> %A) { define <2 x i64> @fcmunez2xdouble(<2 x double> %A) { ; UNE with zero = !OEQ with zero ;CHECK: fcmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0.0 -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp une <2 x double> %A, zeroinitializer %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> ret <2 x i64> %tmp4 @@ -1949,8 +1896,7 @@ define <2 x i32> @fcmunoz2xfloat(<2 x float> %A) { ;CHECK: fcmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0.0 ;CHECK-NEXT: fcmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0.0 ;CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b -;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b %tmp3 = fcmp uno <2 x float> %A, zeroinitializer %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -1961,8 +1907,7 @@ define <4 x i32> @fcmunoz4xfloat(<4 x float> %A) { ;CHECK: fcmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0.0 ;CHECK-NEXT: fcmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0.0 ;CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp uno <4 x float> %A, zeroinitializer %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 @@ -1973,8 +1918,7 @@ define <2 x i64> @fcmunoz2xdouble(<2 x double> %A) { ;CHECK: fcmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0.0 ;CHECK-NEXT: fcmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0.0 ;CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp uno <2 x double> %A, zeroinitializer %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> ret <2 x i64> %tmp4 diff --git a/test/MC/AArch64/neon-diagnostics.s b/test/MC/AArch64/neon-diagnostics.s index 12d56a5fb0..044827e070 100644 --- a/test/MC/AArch64/neon-diagnostics.s +++ b/test/MC/AArch64/neon-diagnostics.s @@ -5089,6 +5089,1040 @@ // CHECK-ERROR: ucvtf d21, s14, #64 // CHECK-ERROR: ^ +//------------------------------------------------------------------------------ +// Element reverse +//------------------------------------------------------------------------------ + rev64 v6.2d, v8.2d + rev32 v30.2s, v31.2s + rev32 v30.4s, v31.4s + rev32 v30.2d, v31.2d + rev16 v21.4h, v1.4h + rev16 v21.8h, v1.8h + rev16 v21.2s, v1.2s + rev16 v21.4s, v1.4s + rev16 v21.2d, v1.2d + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: rev64 v6.2d, v8.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: rev32 v30.2s, v31.2s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: rev32 v30.4s, v31.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: rev32 v30.2d, v31.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: rev16 v21.4h, v1.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: rev16 v21.8h, v1.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: rev16 v21.2s, v1.2s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: rev16 v21.4s, v1.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: rev16 v21.2d, v1.2d +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Signed integer pairwise add long +//------------------------------------------------------------------------------ + + saddlp v3.8h, v21.8h + saddlp v8.8b, v5.8b + saddlp v9.8h, v1.4s + saddlp v0.4s, v1.2d + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: saddlp v3.8h, v21.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: saddlp v8.8b, v5.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: saddlp v9.8h, v1.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: saddlp v0.4s, v1.2d +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Unsigned integer pairwise add long +//------------------------------------------------------------------------------ + + uaddlp v3.8h, v21.8h + uaddlp v8.8b, v5.8b + uaddlp v9.8h, v1.4s + uaddlp v0.4s, v1.2d + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uaddlp v3.8h, v21.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uaddlp v8.8b, v5.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uaddlp v9.8h, v1.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uaddlp v0.4s, v1.2d +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Signed integer pairwise add and accumulate long +//------------------------------------------------------------------------------ + + sadalp v3.16b, v21.16b + sadalp v8.4h, v5.4h + sadalp v9.4s, v1.4s + sadalp v0.4h, v1.2s + sadalp v12.2d, v4.8h + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sadalp v3.16b, v21.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sadalp v8.4h, v5.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sadalp v9.4s, v1.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sadalp v0.4h, v1.2s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sadalp v12.2d, v4.8h +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Unsigned integer pairwise add and accumulate long +//------------------------------------------------------------------------------ + + uadalp v3.16b, v21.16b + uadalp v8.4h, v5.4h + uadalp v9.4s, v1.4s + uadalp v0.4h, v1.2s + uadalp v12.2d, v4.8h + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uadalp v3.16b, v21.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uadalp v8.4h, v5.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uadalp v9.4s, v1.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uadalp v0.4h, v1.2s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uadalp v12.2d, v4.8h +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Signed integer saturating accumulate of unsigned value +//------------------------------------------------------------------------------ + + suqadd v0.16b, v31.8b + suqadd v1.8b, v9.8h + suqadd v13.4h, v21.4s + suqadd v4.2s, v0.2d + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: suqadd v0.16b, v31.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: suqadd v1.8b, v9.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: suqadd v13.4h, v21.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: suqadd v4.2s, v0.2d +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Unsigned integer saturating accumulate of signed value +//------------------------------------------------------------------------------ + + usqadd v0.16b, v31.8b + usqadd v2.8h, v4.4h + usqadd v13.4h, v21.4s + usqadd v4.2s, v0.2d + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: usqadd v0.16b, v31.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: usqadd v2.8h, v4.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: usqadd v13.4h, v21.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: usqadd v4.2s, v0.2d +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Integer saturating absolute +//------------------------------------------------------------------------------ + + sqabs v0.16b, v31.8b + sqabs v2.8h, v4.4h + sqabs v6.4s, v8.2s + sqabs v6.2d, v8.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqabs v0.16b, v31.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqabs v2.8h, v4.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqabs v6.4s, v8.2s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqabs v6.2d, v8.2s +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Signed integer saturating negate +//------------------------------------------------------------------------------ + + sqneg v0.16b, v31.8b + sqneg v2.8h, v4.4h + sqneg v6.4s, v8.2s + sqneg v6.2d, v8.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqneg v0.16b, v31.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqneg v2.8h, v4.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqneg v6.4s, v8.2s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqneg v6.2d, v8.2s +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Integer absolute +//------------------------------------------------------------------------------ + + abs v0.16b, v31.8b + abs v2.8h, v4.4h + abs v6.4s, v8.2s + abs v6.2d, v8.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: abs v0.16b, v31.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: abs v2.8h, v4.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: abs v6.4s, v8.2s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: abs v6.2d, v8.2s +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Integer count leading sign bits +//------------------------------------------------------------------------------ + + cls v0.2d, v31.2d + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: cls v0.2d, v31.2d +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Integer count leading zeros +//------------------------------------------------------------------------------ + + clz v0.2d, v31.2d + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: clz v0.2d, v31.2d +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Population count +//------------------------------------------------------------------------------ + + cnt v2.8h, v4.8h + cnt v6.4s, v8.4s + cnt v6.2d, v8.2d + cnt v13.4h, v21.4h + cnt v4.2s, v0.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: cnt v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: cnt v6.4s, v8.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: cnt v6.2d, v8.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: cnt v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: cnt v4.2s, v0.2s +// CHECK-ERROR: ^ + + +//------------------------------------------------------------------------------ +// Bitwise NOT +//------------------------------------------------------------------------------ + + not v2.8h, v4.8h + not v6.4s, v8.4s + not v6.2d, v8.2d + not v13.4h, v21.4h + not v4.2s, v0.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: not v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: not v6.4s, v8.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: not v6.2d, v8.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: not v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: not v4.2s, v0.2s +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Bitwise reverse +//------------------------------------------------------------------------------ + + rbit v2.8h, v4.8h + rbit v6.4s, v8.4s + rbit v6.2d, v8.2d + rbit v13.4h, v21.4h + rbit v4.2s, v0.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: rbit v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: rbit v6.4s, v8.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: rbit v6.2d, v8.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: rbit v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: rbit v4.2s, v0.2s +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Floating-point absolute +//------------------------------------------------------------------------------ + + fabs v0.16b, v31.16b + fabs v2.8h, v4.8h + fabs v1.8b, v9.8b + fabs v13.4h, v21.4h + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fabs v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fabs v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fabs v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fabs v13.4h, v21.4h +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Floating-point negate +//------------------------------------------------------------------------------ + + fneg v0.16b, v31.16b + fneg v2.8h, v4.8h + fneg v1.8b, v9.8b + fneg v13.4h, v21.4h + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fneg v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fneg v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fneg v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fneg v13.4h, v21.4h +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Integer extract and narrow +//------------------------------------------------------------------------------ + + xtn v0.16b, v31.8h + xtn v2.8h, v4.4s + xtn v6.4s, v8.2d + xtn2 v1.8b, v9.8h + xtn2 v13.4h, v21.4s + xtn2 v4.2s, v0.2d + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: xtn v0.16b, v31.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: xtn v2.8h, v4.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: xtn v6.4s, v8.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: xtn2 v1.8b, v9.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: xtn2 v13.4h, v21.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: xtn2 v4.2s, v0.2d +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Signed integer saturating extract and unsigned narrow +//------------------------------------------------------------------------------ + + sqxtun v0.16b, v31.8h + sqxtun v2.8h, v4.4s + sqxtun v6.4s, v8.2d + sqxtun2 v1.8b, v9.8h + sqxtun2 v13.4h, v21.4s + sqxtun2 v4.2s, v0.2d + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqxtun v0.16b, v31.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqxtun v2.8h, v4.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqxtun v6.4s, v8.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqxtun2 v1.8b, v9.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqxtun2 v13.4h, v21.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqxtun2 v4.2s, v0.2d +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Signed integer saturating extract and narrow +//------------------------------------------------------------------------------ + + sqxtn v0.16b, v31.8h + sqxtn v2.8h, v4.4s + sqxtn v6.4s, v8.2d + sqxtn2 v1.8b, v9.8h + sqxtn2 v13.4h, v21.4s + sqxtn2 v4.2s, v0.2d + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqxtn v0.16b, v31.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqxtn v2.8h, v4.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqxtn v6.4s, v8.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqxtn2 v1.8b, v9.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqxtn2 v13.4h, v21.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqxtn2 v4.2s, v0.2d +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Unsigned integer saturating extract and narrow +//------------------------------------------------------------------------------ + + uqxtn v0.16b, v31.8h + uqxtn v2.8h, v4.4s + uqxtn v6.4s, v8.2d + uqxtn2 v1.8b, v9.8h + uqxtn2 v13.4h, v21.4s + uqxtn2 v4.2s, v0.2d + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uqxtn v0.16b, v31.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uqxtn v2.8h, v4.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uqxtn v6.4s, v8.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uqxtn2 v1.8b, v9.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uqxtn2 v13.4h, v21.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uqxtn2 v4.2s, v0.2d +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Integer shift left long +//------------------------------------------------------------------------------ + + shll2 v2.8h, v4.16b, #7 + shll2 v6.4s, v8.8h, #15 + shll2 v6.2d, v8.4s, #31 + shll v2.8h, v4.16b, #8 + shll v6.4s, v8.8h, #16 + shll v6.2d, v8.4s, #32 + shll v2.8h, v4.8b, #8 + shll v6.4s, v8.4h, #16 + shll v6.2d, v8.2s, #32 + shll2 v2.8h, v4.8b, #5 + shll2 v6.4s, v8.4h, #14 + shll2 v6.2d, v8.2s, #1 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: shll2 v2.8h, v4.16b, #7 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: shll2 v6.4s, v8.8h, #15 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: shll2 v6.2d, v8.4s, #31 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: shll v2.8h, v4.16b, #8 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: shll v6.4s, v8.8h, #16 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: shll v6.2d, v8.4s, #32 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: shll2 v2.8h, v4.8b, #5 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: shll2 v6.4s, v8.4h, #14 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: shll2 v6.2d, v8.2s, #1 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Floating-point convert downsize +//------------------------------------------------------------------------------ + + fcvtn v2.8h, v4.4s + fcvtn v6.4s, v8.2d + fcvtn2 v13.4h, v21.4s + fcvtn2 v4.2s, v0.2d + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtn v2.8h, v4.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtn v6.4s, v8.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtn2 v13.4h, v21.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtn2 v4.2s, v0.2d +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Floating-point convert downsize with inexact +//------------------------------------------------------------------------------ + + fcvtxn v6.4s, v8.2d + fcvtxn2 v4.2s, v0.2d + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtxn v6.4s, v8.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtxn2 v4.2s, v0.2d +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Floating-point convert upsize +//------------------------------------------------------------------------------ + + fcvtl2 v9.4s, v1.4h + fcvtl2 v0.2d, v1.2s + fcvtl v12.4s, v4.8h + fcvtl v17.2d, v28.4s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtl2 v9.4s, v1.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtl2 v0.2d, v1.2s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtl v12.4s, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtl v17.2d, v28.4s +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Floating-point round to integral +//------------------------------------------------------------------------------ + + frintn v0.16b, v31.16b + frintn v2.8h, v4.8h + frintn v1.8b, v9.8b + frintn v13.4h, v21.4h + + frinta v0.16b, v31.16b + frinta v2.8h, v4.8h + frinta v1.8b, v9.8b + frinta v13.4h, v21.4h + + frintp v0.16b, v31.16b + frintp v2.8h, v4.8h + frintp v1.8b, v9.8b + frintp v13.4h, v21.4h + + frintm v0.16b, v31.16b + frintm v2.8h, v4.8h + frintm v1.8b, v9.8b + frintm v13.4h, v21.4h + + frintx v0.16b, v31.16b + frintx v2.8h, v4.8h + frintx v1.8b, v9.8b + frintx v13.4h, v21.4h + + frintz v0.16b, v31.16b + frintz v2.8h, v4.8h + frintz v1.8b, v9.8b + frintz v13.4h, v21.4h + + frinti v0.16b, v31.16b + frinti v2.8h, v4.8h + frinti v1.8b, v9.8b + frinti v13.4h, v21.4h + + fcvtns v0.16b, v31.16b + fcvtns v2.8h, v4.8h + fcvtns v1.8b, v9.8b + fcvtns v13.4h, v21.4h + + fcvtnu v0.16b, v31.16b + fcvtnu v2.8h, v4.8h + fcvtnu v1.8b, v9.8b + fcvtnu v13.4h, v21.4h + + fcvtps v0.16b, v31.16b + fcvtps v2.8h, v4.8h + fcvtps v1.8b, v9.8b + fcvtps v13.4h, v21.4h + + fcvtpu v0.16b, v31.16b + fcvtpu v2.8h, v4.8h + fcvtpu v1.8b, v9.8b + fcvtpu v13.4h, v21.4h + + fcvtms v0.16b, v31.16b + fcvtms v2.8h, v4.8h + fcvtms v1.8b, v9.8b + fcvtms v13.4h, v21.4h + + fcvtmu v0.16b, v31.16b + fcvtmu v2.8h, v4.8h + fcvtmu v1.8b, v9.8b + fcvtmu v13.4h, v21.4h + + fcvtzs v0.16b, v31.16b + fcvtzs v2.8h, v4.8h + fcvtzs v1.8b, v9.8b + fcvtzs v13.4h, v21.4h + + fcvtzu v0.16b, v31.16b + fcvtzu v2.8h, v4.8h + fcvtzu v1.8b, v9.8b + fcvtzu v13.4h, v21.4h + + fcvtas v0.16b, v31.16b + fcvtas v2.8h, v4.8h + fcvtas v1.8b, v9.8b + fcvtas v13.4h, v21.4h + + fcvtau v0.16b, v31.16b + fcvtau v2.8h, v4.8h + fcvtau v1.8b, v9.8b + fcvtau v13.4h, v21.4h + + urecpe v0.16b, v31.16b + urecpe v2.8h, v4.8h + urecpe v1.8b, v9.8b + urecpe v13.4h, v21.4h + urecpe v1.2d, v9.2d + + ursqrte v0.16b, v31.16b + ursqrte v2.8h, v4.8h + ursqrte v1.8b, v9.8b + ursqrte v13.4h, v21.4h + ursqrte v1.2d, v9.2d + + scvtf v0.16b, v31.16b + scvtf v2.8h, v4.8h + scvtf v1.8b, v9.8b + scvtf v13.4h, v21.4h + + ucvtf v0.16b, v31.16b + ucvtf v2.8h, v4.8h + ucvtf v1.8b, v9.8b + ucvtf v13.4h, v21.4h + + frecpe v0.16b, v31.16b + frecpe v2.8h, v4.8h + frecpe v1.8b, v9.8b + frecpe v13.4h, v21.4h + + frsqrte v0.16b, v31.16b + frsqrte v2.8h, v4.8h + frsqrte v1.8b, v9.8b + frsqrte v13.4h, v21.4h + + fsqrt v0.16b, v31.16b + fsqrt v2.8h, v4.8h + fsqrt v1.8b, v9.8b + fsqrt v13.4h, v21.4h + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frintn v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frintn v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frintn v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frintn v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frinta v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frinta v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frinta v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frinta v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frintp v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frintp v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frintp v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frintp v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frintm v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frintm v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frintm v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frintm v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frintx v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frintx v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frintx v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frintx v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frintz v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frintz v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frintz v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frintz v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frinti v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frinti v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frinti v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frinti v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtns v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtns v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtns v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtns v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtnu v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtnu v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtnu v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtnu v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtps v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtps v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtps v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtps v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtpu v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtpu v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtpu v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtpu v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtms v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtms v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtms v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtms v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtmu v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtmu v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtmu v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtmu v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtzs v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtzs v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtzs v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtzs v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtzu v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtzu v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtzu v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtzu v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtas v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtas v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtas v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtas v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtau v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtau v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtau v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtau v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: urecpe v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: urecpe v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: urecpe v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: urecpe v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: urecpe v1.2d, v9.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ursqrte v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ursqrte v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ursqrte v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ursqrte v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ursqrte v1.2d, v9.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: scvtf v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: scvtf v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: scvtf v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: scvtf v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ucvtf v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ucvtf v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ucvtf v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ucvtf v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frecpe v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frecpe v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frecpe v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frecpe v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frsqrte v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frsqrte v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frsqrte v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frsqrte v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fsqrt v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fsqrt v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fsqrt v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fsqrt v13.4h, v21.4h +// CHECK-ERROR: ^ + //---------------------------------------------------------------------- // Scalar Floating-point Convert To Signed Fixed-point (Immediate) //---------------------------------------------------------------------- -- cgit v1.2.3