From ace0c2fad7c581367cc2519e1d773bca37fc9fec Mon Sep 17 00:00:00 2001 From: Nadav Rotem Date: Mon, 24 Dec 2012 09:40:33 +0000 Subject: Some x86 instructions can load/store one of the operands to memory. On SSE, this memory needs to be aligned. When these instructions are encoded in VEX (on AVX) there is no such requirement. This changes the folding tables and removes the alignment restrictions from VEX-encoded instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171024 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/X86/fold-vex.ll | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 test/CodeGen/X86/fold-vex.ll (limited to 'test') diff --git a/test/CodeGen/X86/fold-vex.ll b/test/CodeGen/X86/fold-vex.ll new file mode 100644 index 0000000000..60e500b419 --- /dev/null +++ b/test/CodeGen/X86/fold-vex.ll @@ -0,0 +1,16 @@ +; RUN: llc < %s -mcpu=corei7-avx -march=x86-64 | FileCheck %s + +;CHECK: @test +; No need to load from memory. The operand will be loaded as part of th AND instr. +;CHECK-NOT: vmovaps +;CHECK: vandps +;CHECK: ret + +define void @test1(<8 x i32>* %p0, <8 x i32> %in1) nounwind { +entry: + %in0 = load <8 x i32>* %p0, align 2 + %a = and <8 x i32> %in0, %in1 + store <8 x i32> %a, <8 x i32>* undef + ret void +} + -- cgit v1.2.3