From c6df9883da99915d1cfa491b381ffa703c61ed90 Mon Sep 17 00:00:00 2001 From: Bill Wendling Date: Thu, 14 Apr 2011 01:11:51 +0000 Subject: Have the X86 back-end emit the alias instead of what's being aliased. In most cases, it's much nicer and more informative reading the alias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129497 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/X86/2006-11-17-IllegalMove.ll | 2 +- test/CodeGen/X86/2007-08-10-SignExtSubreg.ll | 2 +- test/CodeGen/X86/2007-09-27-LDIntrinsics.ll | 4 +- test/CodeGen/X86/2008-08-17-UComiCodeGenBug.ll | 7 +- test/CodeGen/X86/2009-06-05-VZextByteShort.ll | 13 ++- test/CodeGen/X86/anyext.ll | 6 +- test/CodeGen/X86/avx-intrinsics-x86.ll | 64 ++++++------- test/CodeGen/X86/bool-zext.ll | 6 +- test/CodeGen/X86/cmov.ll | 4 +- test/CodeGen/X86/cmp.ll | 4 +- test/CodeGen/X86/fast-isel-gep.ll | 4 +- test/CodeGen/X86/fp-stack-compare.ll | 14 +-- test/CodeGen/X86/h-register-addressing-32.ll | 2 +- test/CodeGen/X86/h-registers-0.ll | 6 +- test/CodeGen/X86/h-registers-2.ll | 2 +- test/CodeGen/X86/inline-asm-mrv.ll | 2 +- test/CodeGen/X86/masked-iv-unsafe.ll | 2 +- test/CodeGen/X86/pr3366.ll | 3 +- test/CodeGen/X86/promote-assert-zext.ll | 2 +- test/CodeGen/X86/promote-i16.ll | 4 +- test/CodeGen/X86/select.ll | 2 +- test/CodeGen/X86/setcc.ll | 2 +- test/CodeGen/X86/sext-ret-val.ll | 2 +- test/CodeGen/X86/sext-subreg.ll | 2 +- test/CodeGen/X86/shl_elim.ll | 2 +- test/CodeGen/X86/umul-with-overflow.ll | 2 +- test/CodeGen/X86/vshift-4.ll | 2 +- test/CodeGen/X86/widen_conv-2.ll | 4 +- test/CodeGen/X86/x86-64-shortint.ll | 2 +- test/MC/X86/x86-32.s | 18 ++-- test/MC/X86/x86-64.s | 122 ++++++++++++------------- 31 files changed, 161 insertions(+), 152 deletions(-) (limited to 'test') diff --git a/test/CodeGen/X86/2006-11-17-IllegalMove.ll b/test/CodeGen/X86/2006-11-17-IllegalMove.ll index affb7afb1c..091a340b8a 100644 --- a/test/CodeGen/X86/2006-11-17-IllegalMove.ll +++ b/test/CodeGen/X86/2006-11-17-IllegalMove.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=x86-64 > %t ; RUN: grep movb %t | count 2 -; RUN: grep {movzb\[wl\]} %t +; RUN: grep {movzx} %t define void @handle_vector_size_attribute() nounwind { diff --git a/test/CodeGen/X86/2007-08-10-SignExtSubreg.ll b/test/CodeGen/X86/2007-08-10-SignExtSubreg.ll index e93092f355..a492f8d37f 100644 --- a/test/CodeGen/X86/2007-08-10-SignExtSubreg.ll +++ b/test/CodeGen/X86/2007-08-10-SignExtSubreg.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 | grep {movsbl} +; RUN: llc < %s -march=x86 | grep {movsx} @X = global i32 0 ; [#uses=1] diff --git a/test/CodeGen/X86/2007-09-27-LDIntrinsics.ll b/test/CodeGen/X86/2007-09-27-LDIntrinsics.ll index 4d6971586c..b4a986ff77 100644 --- a/test/CodeGen/X86/2007-09-27-LDIntrinsics.ll +++ b/test/CodeGen/X86/2007-09-27-LDIntrinsics.ll @@ -22,8 +22,8 @@ entry: ; CHECK: bar: ; CHECK: fldt 4(%esp) ; CHECK-NEXT: fld %st(0) -; CHECK-NEXT: fmul %st(1) -; CHECK-NEXT: fmulp %st(1) +; CHECK-NEXT: fmul %st(1), %st(0) +; CHECK-NEXT: fmulp ; CHECK-NEXT: ret } diff --git a/test/CodeGen/X86/2008-08-17-UComiCodeGenBug.ll b/test/CodeGen/X86/2008-08-17-UComiCodeGenBug.ll index 32f6ca0ce0..9cc05262e0 100644 --- a/test/CodeGen/X86/2008-08-17-UComiCodeGenBug.ll +++ b/test/CodeGen/X86/2008-08-17-UComiCodeGenBug.ll @@ -1,9 +1,10 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep movzbl +; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s define i32 @foo(<4 x float> %a, <4 x float> %b) nounwind { entry: - tail call i32 @llvm.x86.sse.ucomige.ss( <4 x float> %a, <4 x float> %b ) nounwind readnone - ret i32 %0 +; CHECK: movzx + tail call i32 @llvm.x86.sse.ucomige.ss( <4 x float> %a, <4 x float> %b ) nounwind readnone + ret i32 %0 } declare i32 @llvm.x86.sse.ucomige.ss(<4 x float>, <4 x float>) nounwind readnone diff --git a/test/CodeGen/X86/2009-06-05-VZextByteShort.ll b/test/CodeGen/X86/2009-06-05-VZextByteShort.ll index 5c514805e4..1d29fea30d 100644 --- a/test/CodeGen/X86/2009-06-05-VZextByteShort.ll +++ b/test/CodeGen/X86/2009-06-05-VZextByteShort.ll @@ -1,9 +1,8 @@ -; RUN: llc < %s -march=x86 -mattr=+mmx,+sse2 > %t1 -; RUN: grep movzwl %t1 | count 2 -; RUN: grep movzbl %t1 | count 2 -; RUN: grep movd %t1 | count 4 +; RUN: llc < %s -march=x86 -mattr=+mmx,+sse2 | FileCheck %s define <4 x i16> @a(i32* %x1) nounwind { +; CHECK: movzx +; CHECK-NEXT: movd %x2 = load i32* %x1 %x3 = lshr i32 %x2, 1 %x = trunc i32 %x3 to i16 @@ -12,6 +11,8 @@ define <4 x i16> @a(i32* %x1) nounwind { } define <8 x i16> @b(i32* %x1) nounwind { +; CHECK: movzx +; CHECK-NEXT: movd %x2 = load i32* %x1 %x3 = lshr i32 %x2, 1 %x = trunc i32 %x3 to i16 @@ -20,6 +21,8 @@ define <8 x i16> @b(i32* %x1) nounwind { } define <8 x i8> @c(i32* %x1) nounwind { +; CHECK: movzx +; CHECK-NEXT: movd %x2 = load i32* %x1 %x3 = lshr i32 %x2, 1 %x = trunc i32 %x3 to i8 @@ -28,6 +31,8 @@ define <8 x i8> @c(i32* %x1) nounwind { } define <16 x i8> @d(i32* %x1) nounwind { +; CHECK: movzx +; CHECK-NEXT: movd %x2 = load i32* %x1 %x3 = lshr i32 %x2, 1 %x = trunc i32 %x3 to i8 diff --git a/test/CodeGen/X86/anyext.ll b/test/CodeGen/X86/anyext.ll index 106fe83661..32a48fbedc 100644 --- a/test/CodeGen/X86/anyext.ll +++ b/test/CodeGen/X86/anyext.ll @@ -1,8 +1,10 @@ -; RUN: llc < %s -march=x86-64 | grep movzbl | count 2 +; RUN: llc < %s -march=x86-64 | FileCheck %s -; Use movzbl to avoid partial-register updates. +; Use movzbl (aliased as movzx) to avoid partial-register updates. define i32 @foo(i32 %p, i8 zeroext %x) nounwind { +; CHECK: movzx %dil, %eax +; CHECK: movzx %al, %eax %q = trunc i32 %p to i8 %r = udiv i8 %q, %x %s = zext i8 %r to i32 diff --git a/test/CodeGen/X86/avx-intrinsics-x86.ll b/test/CodeGen/X86/avx-intrinsics-x86.ll index 5201688686..051be285e1 100644 --- a/test/CodeGen/X86/avx-intrinsics-x86.ll +++ b/test/CodeGen/X86/avx-intrinsics-x86.ll @@ -75,7 +75,7 @@ declare <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double>, <2 x double>, i8) nounw define i32 @test_x86_sse2_comieq_sd(<2 x double> %a0, <2 x double> %a1) { ; CHECK: vcomisd ; CHECK: sete - ; CHECK: movzbl + ; CHECK: movzx %res = call i32 @llvm.x86.sse2.comieq.sd(<2 x double> %a0, <2 x double> %a1) ; [#uses=1] ret i32 %res } @@ -85,7 +85,7 @@ declare i32 @llvm.x86.sse2.comieq.sd(<2 x double>, <2 x double>) nounwind readno define i32 @test_x86_sse2_comige_sd(<2 x double> %a0, <2 x double> %a1) { ; CHECK: vcomisd ; CHECK: setae - ; CHECK: movzbl + ; CHECK: movzx %res = call i32 @llvm.x86.sse2.comige.sd(<2 x double> %a0, <2 x double> %a1) ; [#uses=1] ret i32 %res } @@ -95,7 +95,7 @@ declare i32 @llvm.x86.sse2.comige.sd(<2 x double>, <2 x double>) nounwind readno define i32 @test_x86_sse2_comigt_sd(<2 x double> %a0, <2 x double> %a1) { ; CHECK: vcomisd ; CHECK: seta - ; CHECK: movzbl + ; CHECK: movzx %res = call i32 @llvm.x86.sse2.comigt.sd(<2 x double> %a0, <2 x double> %a1) ; [#uses=1] ret i32 %res } @@ -105,7 +105,7 @@ declare i32 @llvm.x86.sse2.comigt.sd(<2 x double>, <2 x double>) nounwind readno define i32 @test_x86_sse2_comile_sd(<2 x double> %a0, <2 x double> %a1) { ; CHECK: vcomisd ; CHECK: setbe - ; CHECK: movzbl + ; CHECK: movzx %res = call i32 @llvm.x86.sse2.comile.sd(<2 x double> %a0, <2 x double> %a1) ; [#uses=1] ret i32 %res } @@ -125,7 +125,7 @@ declare i32 @llvm.x86.sse2.comilt.sd(<2 x double>, <2 x double>) nounwind readno define i32 @test_x86_sse2_comineq_sd(<2 x double> %a0, <2 x double> %a1) { ; CHECK: vcomisd ; CHECK: setne - ; CHECK: movzbl + ; CHECK: movzx %res = call i32 @llvm.x86.sse2.comineq.sd(<2 x double> %a0, <2 x double> %a1) ; [#uses=1] ret i32 %res } @@ -786,7 +786,7 @@ declare <2 x double> @llvm.x86.sse2.sub.sd(<2 x double>, <2 x double>) nounwind define i32 @test_x86_sse2_ucomieq_sd(<2 x double> %a0, <2 x double> %a1) { ; CHECK: vucomisd ; CHECK: sete - ; CHECK: movzbl + ; CHECK: movzx %res = call i32 @llvm.x86.sse2.ucomieq.sd(<2 x double> %a0, <2 x double> %a1) ; [#uses=1] ret i32 %res } @@ -796,7 +796,7 @@ declare i32 @llvm.x86.sse2.ucomieq.sd(<2 x double>, <2 x double>) nounwind readn define i32 @test_x86_sse2_ucomige_sd(<2 x double> %a0, <2 x double> %a1) { ; CHECK: vucomisd ; CHECK: setae - ; CHECK: movzbl + ; CHECK: movzx %res = call i32 @llvm.x86.sse2.ucomige.sd(<2 x double> %a0, <2 x double> %a1) ; [#uses=1] ret i32 %res } @@ -806,7 +806,7 @@ declare i32 @llvm.x86.sse2.ucomige.sd(<2 x double>, <2 x double>) nounwind readn define i32 @test_x86_sse2_ucomigt_sd(<2 x double> %a0, <2 x double> %a1) { ; CHECK: vucomisd ; CHECK: seta - ; CHECK: movzbl + ; CHECK: movzx %res = call i32 @llvm.x86.sse2.ucomigt.sd(<2 x double> %a0, <2 x double> %a1) ; [#uses=1] ret i32 %res } @@ -816,7 +816,7 @@ declare i32 @llvm.x86.sse2.ucomigt.sd(<2 x double>, <2 x double>) nounwind readn define i32 @test_x86_sse2_ucomile_sd(<2 x double> %a0, <2 x double> %a1) { ; CHECK: vucomisd ; CHECK: setbe - ; CHECK: movzbl + ; CHECK: movzx %res = call i32 @llvm.x86.sse2.ucomile.sd(<2 x double> %a0, <2 x double> %a1) ; [#uses=1] ret i32 %res } @@ -835,7 +835,7 @@ declare i32 @llvm.x86.sse2.ucomilt.sd(<2 x double>, <2 x double>) nounwind readn define i32 @test_x86_sse2_ucomineq_sd(<2 x double> %a0, <2 x double> %a1) { ; CHECK: vucomisd ; CHECK: setne - ; CHECK: movzbl + ; CHECK: movzx %res = call i32 @llvm.x86.sse2.ucomineq.sd(<2 x double> %a0, <2 x double> %a1) ; [#uses=1] ret i32 %res } @@ -1192,7 +1192,7 @@ declare i32 @llvm.x86.sse41.ptestc(<4 x float>, <4 x float>) nounwind readnone define i32 @test_x86_sse41_ptestnzc(<4 x float> %a0, <4 x float> %a1) { ; CHECK: vptest ; CHECK: seta - ; CHECK: movzbl + ; CHECK: movzx %res = call i32 @llvm.x86.sse41.ptestnzc(<4 x float> %a0, <4 x float> %a1) ; [#uses=1] ret i32 %res } @@ -1202,7 +1202,7 @@ declare i32 @llvm.x86.sse41.ptestnzc(<4 x float>, <4 x float>) nounwind readnone define i32 @test_x86_sse41_ptestz(<4 x float> %a0, <4 x float> %a1) { ; CHECK: vptest ; CHECK: sete - ; CHECK: movzbl + ; CHECK: movzx %res = call i32 @llvm.x86.sse41.ptestz(<4 x float> %a0, <4 x float> %a1) ; [#uses=1] ret i32 %res } @@ -1414,7 +1414,7 @@ declare <4 x float> @llvm.x86.sse.cmp.ss(<4 x float>, <4 x float>, i8) nounwind define i32 @test_x86_sse_comieq_ss(<4 x float> %a0, <4 x float> %a1) { ; CHECK: vcomiss ; CHECK: sete - ; CHECK: movzbl + ; CHECK: movzx %res = call i32 @llvm.x86.sse.comieq.ss(<4 x float> %a0, <4 x float> %a1) ; [#uses=1] ret i32 %res } @@ -1424,7 +1424,7 @@ declare i32 @llvm.x86.sse.comieq.ss(<4 x float>, <4 x float>) nounwind readnone define i32 @test_x86_sse_comige_ss(<4 x float> %a0, <4 x float> %a1) { ; CHECK: vcomiss ; CHECK: setae - ; CHECK: movzbl + ; CHECK: movzx %res = call i32 @llvm.x86.sse.comige.ss(<4 x float> %a0, <4 x float> %a1) ; [#uses=1] ret i32 %res } @@ -1434,7 +1434,7 @@ declare i32 @llvm.x86.sse.comige.ss(<4 x float>, <4 x float>) nounwind readnone define i32 @test_x86_sse_comigt_ss(<4 x float> %a0, <4 x float> %a1) { ; CHECK: vcomiss ; CHECK: seta - ; CHECK: movzbl + ; CHECK: movzx %res = call i32 @llvm.x86.sse.comigt.ss(<4 x float> %a0, <4 x float> %a1) ; [#uses=1] ret i32 %res } @@ -1444,7 +1444,7 @@ declare i32 @llvm.x86.sse.comigt.ss(<4 x float>, <4 x float>) nounwind readnone define i32 @test_x86_sse_comile_ss(<4 x float> %a0, <4 x float> %a1) { ; CHECK: vcomiss ; CHECK: setbe - ; CHECK: movzbl + ; CHECK: movzx %res = call i32 @llvm.x86.sse.comile.ss(<4 x float> %a0, <4 x float> %a1) ; [#uses=1] ret i32 %res } @@ -1463,7 +1463,7 @@ declare i32 @llvm.x86.sse.comilt.ss(<4 x float>, <4 x float>) nounwind readnone define i32 @test_x86_sse_comineq_ss(<4 x float> %a0, <4 x float> %a1) { ; CHECK: vcomiss ; CHECK: setne - ; CHECK: movzbl + ; CHECK: movzx %res = call i32 @llvm.x86.sse.comineq.ss(<4 x float> %a0, <4 x float> %a1) ; [#uses=1] ret i32 %res } @@ -1655,7 +1655,7 @@ declare <4 x float> @llvm.x86.sse.sub.ss(<4 x float>, <4 x float>) nounwind read define i32 @test_x86_sse_ucomieq_ss(<4 x float> %a0, <4 x float> %a1) { ; CHECK: vucomiss ; CHECK: sete - ; CHECK: movzbl + ; CHECK: movzx %res = call i32 @llvm.x86.sse.ucomieq.ss(<4 x float> %a0, <4 x float> %a1) ; [#uses=1] ret i32 %res } @@ -1665,7 +1665,7 @@ declare i32 @llvm.x86.sse.ucomieq.ss(<4 x float>, <4 x float>) nounwind readnone define i32 @test_x86_sse_ucomige_ss(<4 x float> %a0, <4 x float> %a1) { ; CHECK: vucomiss ; CHECK: setae - ; CHECK: movzbl + ; CHECK: movzx %res = call i32 @llvm.x86.sse.ucomige.ss(<4 x float> %a0, <4 x float> %a1) ; [#uses=1] ret i32 %res } @@ -1675,7 +1675,7 @@ declare i32 @llvm.x86.sse.ucomige.ss(<4 x float>, <4 x float>) nounwind readnone define i32 @test_x86_sse_ucomigt_ss(<4 x float> %a0, <4 x float> %a1) { ; CHECK: vucomiss ; CHECK: seta - ; CHECK: movzbl + ; CHECK: movzx %res = call i32 @llvm.x86.sse.ucomigt.ss(<4 x float> %a0, <4 x float> %a1) ; [#uses=1] ret i32 %res } @@ -1685,7 +1685,7 @@ declare i32 @llvm.x86.sse.ucomigt.ss(<4 x float>, <4 x float>) nounwind readnone define i32 @test_x86_sse_ucomile_ss(<4 x float> %a0, <4 x float> %a1) { ; CHECK: vucomiss ; CHECK: setbe - ; CHECK: movzbl + ; CHECK: movzx %res = call i32 @llvm.x86.sse.ucomile.ss(<4 x float> %a0, <4 x float> %a1) ; [#uses=1] ret i32 %res } @@ -1704,7 +1704,7 @@ declare i32 @llvm.x86.sse.ucomilt.ss(<4 x float>, <4 x float>) nounwind readnone define i32 @test_x86_sse_ucomineq_ss(<4 x float> %a0, <4 x float> %a1) { ; CHECK: vucomiss ; CHECK: setne - ; CHECK: movzbl + ; CHECK: movzx %res = call i32 @llvm.x86.sse.ucomineq.ss(<4 x float> %a0, <4 x float> %a1) ; [#uses=1] ret i32 %res } @@ -2179,7 +2179,7 @@ declare i32 @llvm.x86.avx.ptestc.256(<4 x i64>, <4 x i64>) nounwind readnone define i32 @test_x86_avx_ptestnzc_256(<4 x i64> %a0, <4 x i64> %a1) { ; CHECK: vptest ; CHECK: seta - ; CHECK: movzbl + ; CHECK: movzx %res = call i32 @llvm.x86.avx.ptestnzc.256(<4 x i64> %a0, <4 x i64> %a1) ; [#uses=1] ret i32 %res } @@ -2189,7 +2189,7 @@ declare i32 @llvm.x86.avx.ptestnzc.256(<4 x i64>, <4 x i64>) nounwind readnone define i32 @test_x86_avx_ptestz_256(<4 x i64> %a0, <4 x i64> %a1) { ; CHECK: vptest ; CHECK: sete - ; CHECK: movzbl + ; CHECK: movzx %res = call i32 @llvm.x86.avx.ptestz.256(<4 x i64> %a0, <4 x i64> %a1) ; [#uses=1] ret i32 %res } @@ -2483,7 +2483,7 @@ declare i32 @llvm.x86.avx.vtestc.ps.256(<8 x float>, <8 x float>) nounwind readn define i32 @test_x86_avx_vtestnzc_pd(<2 x double> %a0, <2 x double> %a1) { ; CHECK: vtestpd ; CHECK: seta - ; CHECK: movzbl + ; CHECK: movzx %res = call i32 @llvm.x86.avx.vtestnzc.pd(<2 x double> %a0, <2 x double> %a1) ; [#uses=1] ret i32 %res } @@ -2493,7 +2493,7 @@ declare i32 @llvm.x86.avx.vtestnzc.pd(<2 x double>, <2 x double>) nounwind readn define i32 @test_x86_avx_vtestnzc_pd_256(<4 x double> %a0, <4 x double> %a1) { ; CHECK: vtestpd ; CHECK: seta - ; CHECK: movzbl + ; CHECK: movzx %res = call i32 @llvm.x86.avx.vtestnzc.pd.256(<4 x double> %a0, <4 x double> %a1) ; [#uses=1] ret i32 %res } @@ -2503,7 +2503,7 @@ declare i32 @llvm.x86.avx.vtestnzc.pd.256(<4 x double>, <4 x double>) nounwind r define i32 @test_x86_avx_vtestnzc_ps(<4 x float> %a0, <4 x float> %a1) { ; CHECK: vtestps ; CHECK: seta - ; CHECK: movzbl + ; CHECK: movzx %res = call i32 @llvm.x86.avx.vtestnzc.ps(<4 x float> %a0, <4 x float> %a1) ; [#uses=1] ret i32 %res } @@ -2513,7 +2513,7 @@ declare i32 @llvm.x86.avx.vtestnzc.ps(<4 x float>, <4 x float>) nounwind readnon define i32 @test_x86_avx_vtestnzc_ps_256(<8 x float> %a0, <8 x float> %a1) { ; CHECK: vtestps ; CHECK: seta - ; CHECK: movzbl + ; CHECK: movzx %res = call i32 @llvm.x86.avx.vtestnzc.ps.256(<8 x float> %a0, <8 x float> %a1) ; [#uses=1] ret i32 %res } @@ -2523,7 +2523,7 @@ declare i32 @llvm.x86.avx.vtestnzc.ps.256(<8 x float>, <8 x float>) nounwind rea define i32 @test_x86_avx_vtestz_pd(<2 x double> %a0, <2 x double> %a1) { ; CHECK: vtestpd ; CHECK: sete - ; CHECK: movzbl + ; CHECK: movzx %res = call i32 @llvm.x86.avx.vtestz.pd(<2 x double> %a0, <2 x double> %a1) ; [#uses=1] ret i32 %res } @@ -2533,7 +2533,7 @@ declare i32 @llvm.x86.avx.vtestz.pd(<2 x double>, <2 x double>) nounwind readnon define i32 @test_x86_avx_vtestz_pd_256(<4 x double> %a0, <4 x double> %a1) { ; CHECK: vtestpd ; CHECK: sete - ; CHECK: movzbl + ; CHECK: movzx %res = call i32 @llvm.x86.avx.vtestz.pd.256(<4 x double> %a0, <4 x double> %a1) ; [#uses=1] ret i32 %res } @@ -2543,7 +2543,7 @@ declare i32 @llvm.x86.avx.vtestz.pd.256(<4 x double>, <4 x double>) nounwind rea define i32 @test_x86_avx_vtestz_ps(<4 x float> %a0, <4 x float> %a1) { ; CHECK: vtestps ; CHECK: sete - ; CHECK: movzbl + ; CHECK: movzx %res = call i32 @llvm.x86.avx.vtestz.ps(<4 x float> %a0, <4 x float> %a1) ; [#uses=1] ret i32 %res } @@ -2553,7 +2553,7 @@ declare i32 @llvm.x86.avx.vtestz.ps(<4 x float>, <4 x float>) nounwind readnone define i32 @test_x86_avx_vtestz_ps_256(<8 x float> %a0, <8 x float> %a1) { ; CHECK: vtestps ; CHECK: sete - ; CHECK: movzbl + ; CHECK: movzx %res = call i32 @llvm.x86.avx.vtestz.ps.256(<8 x float> %a0, <8 x float> %a1) ; [#uses=1] ret i32 %res } diff --git a/test/CodeGen/X86/bool-zext.ll b/test/CodeGen/X86/bool-zext.ll index d2c30c64f2..91e36b0d53 100644 --- a/test/CodeGen/X86/bool-zext.ll +++ b/test/CodeGen/X86/bool-zext.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=x86-64 | FileCheck %s ; CHECK: @bar1 -; CHECK: movzbl +; CHECK: movzx ; CHECK: callq define void @bar1(i1 zeroext %v1) nounwind ssp { entry: @@ -11,7 +11,7 @@ entry: } ; CHECK: @bar2 -; CHECK-NOT: movzbl +; CHECK-NOT: movzx ; CHECK: callq define void @bar2(i8 zeroext %v1) nounwind ssp { entry: @@ -22,7 +22,7 @@ entry: ; CHECK: @bar3 ; CHECK: callq -; CHECK-NOT: movzbl +; CHECK-NOT: movzx ; CHECK-NOT: and ; CHECK: ret define zeroext i1 @bar3() nounwind ssp { diff --git a/test/CodeGen/X86/cmov.ll b/test/CodeGen/X86/cmov.ll index 39d9d1e9ec..2e71ef20cf 100644 --- a/test/CodeGen/X86/cmov.ll +++ b/test/CodeGen/X86/cmov.ll @@ -121,7 +121,7 @@ define i32 @test5(i32* nocapture %P) nounwind readonly { entry: ; CHECK: test5: ; CHECK: setg %al -; CHECK: movzbl %al, %eax +; CHECK: movzx %al, %eax ; CHECK: orl $-2, %eax ; CHECK: ret @@ -135,7 +135,7 @@ define i32 @test6(i32* nocapture %P) nounwind readonly { entry: ; CHECK: test6: ; CHECK: setl %al -; CHECK: movzbl %al, %eax +; CHECK: movzx %al, %eax ; CHECK: leal 4(%rax,%rax,8), %eax ; CHECK: ret %0 = load i32* %P, align 4 ; [#uses=1] diff --git a/test/CodeGen/X86/cmp.ll b/test/CodeGen/X86/cmp.ll index ef5e353e9f..6e88fc1cbe 100644 --- a/test/CodeGen/X86/cmp.ll +++ b/test/CodeGen/X86/cmp.ll @@ -38,7 +38,7 @@ define i64 @test3(i64 %x) nounwind { ; CHECK: test3: ; CHECK: testq %rdi, %rdi ; CHECK: sete %al -; CHECK: movzbl %al, %eax +; CHECK: movzx %al, %eax ; CHECK: ret } @@ -49,7 +49,7 @@ define i64 @test4(i64 %x) nounwind { ; CHECK: test4: ; CHECK: testq %rdi, %rdi ; CHECK: setle %al -; CHECK: movzbl %al, %eax +; CHECK: movzx %al, %eax ; CHECK: ret } diff --git a/test/CodeGen/X86/fast-isel-gep.ll b/test/CodeGen/X86/fast-isel-gep.ll index 48abfd0f26..ebefd74f19 100644 --- a/test/CodeGen/X86/fast-isel-gep.ll +++ b/test/CodeGen/X86/fast-isel-gep.ll @@ -14,7 +14,7 @@ define i32 @test1(i32 %t3, i32* %t1) nounwind { ; X32: ret ; X64: test1: -; X64: movslq %e[[A0:di|cx]], %rax +; X64: movsx %e[[A0:di|cx]], %rax ; X64: movl (%r[[A1:si|dx]],%rax,4), %eax ; X64: ret @@ -81,7 +81,7 @@ define i64 @test5(i8* %A, i32 %I, i64 %B) nounwind { %v11 = add i64 %B, %v10 ret i64 %v11 ; X64: test5: -; X64: movslq %e[[A1]], %rax +; X64: movsx %e[[A1]], %rax ; X64-NEXT: movq (%r[[A0]],%rax), %rax ; X64-NEXT: addq %{{rdx|r8}}, %rax ; X64-NEXT: ret diff --git a/test/CodeGen/X86/fp-stack-compare.ll b/test/CodeGen/X86/fp-stack-compare.ll index b216914d23..f3998b67f6 100644 --- a/test/CodeGen/X86/fp-stack-compare.ll +++ b/test/CodeGen/X86/fp-stack-compare.ll @@ -1,11 +1,11 @@ -; RUN: llc < %s -march=x86 -mcpu=i386 | grep {fucompi.*st.\[12\]} +; RUN: llc < %s -march=x86 -mcpu=i386 | FileCheck %s ; PR1012 define float @foo(float* %col.2.0) { - %tmp = load float* %col.2.0 ; [#uses=3] - %tmp16 = fcmp olt float %tmp, 0.000000e+00 ; [#uses=1] - %tmp20 = fsub float -0.000000e+00, %tmp ; [#uses=1] - %iftmp.2.0 = select i1 %tmp16, float %tmp20, float %tmp ; [#uses=1] - ret float %iftmp.2.0 +; CHECK: fucompi + %tmp = load float* %col.2.0 + %tmp16 = fcmp olt float %tmp, 0.000000e+00 + %tmp20 = fsub float -0.000000e+00, %tmp + %iftmp.2.0 = select i1 %tmp16, float %tmp20, float %tmp + ret float %iftmp.2.0 } - diff --git a/test/CodeGen/X86/h-register-addressing-32.ll b/test/CodeGen/X86/h-register-addressing-32.ll index 76ffd66524..e312bcc2e2 100644 --- a/test/CodeGen/X86/h-register-addressing-32.ll +++ b/test/CodeGen/X86/h-register-addressing-32.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 | grep {movzbl %\[abcd\]h,} | count 7 +; RUN: llc < %s -march=x86 | grep {movzx %\[abcd\]h,} | count 7 ; Use h-register extract and zero-extend. diff --git a/test/CodeGen/X86/h-registers-0.ll b/test/CodeGen/X86/h-registers-0.ll index cdc75af92e..b477d7759c 100644 --- a/test/CodeGen/X86/h-registers-0.ll +++ b/test/CodeGen/X86/h-registers-0.ll @@ -70,7 +70,7 @@ define i64 @qux64(i64 inreg %x) nounwind { ; WIN64: movzbl %ch, %eax ; X86-32: qux64: -; X86-32: movzbl %ah, %eax +; X86-32: movzx %ah, %eax %t0 = lshr i64 %x, 8 %t1 = and i64 %t0, 255 ret i64 %t1 @@ -85,7 +85,7 @@ define i32 @qux32(i32 inreg %x) nounwind { ; WIN64: movzbl %ch, %eax ; X86-32: qux32: -; X86-32: movzbl %ah, %eax +; X86-32: movzx %ah, %eax %t0 = lshr i32 %x, 8 %t1 = and i32 %t0, 255 ret i32 %t1 @@ -100,7 +100,7 @@ define i16 @qux16(i16 inreg %x) nounwind { ; WIN64: movzbl %ch, %eax ; X86-32: qux16: -; X86-32: movzbl %ah, %eax +; X86-32: movzx %ah, %eax %t0 = lshr i16 %x, 8 ret i16 %t0 } diff --git a/test/CodeGen/X86/h-registers-2.ll b/test/CodeGen/X86/h-registers-2.ll index 16e13f8396..702e90bf5e 100644 --- a/test/CodeGen/X86/h-registers-2.ll +++ b/test/CodeGen/X86/h-registers-2.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=x86 > %t -; RUN: grep {movzbl %\[abcd\]h,} %t | count 1 +; RUN: grep {movzx %\[abcd\]h,} %t | count 1 ; RUN: grep {shll \$3,} %t | count 1 ; Use an h register, but don't omit the explicit shift for diff --git a/test/CodeGen/X86/inline-asm-mrv.ll b/test/CodeGen/X86/inline-asm-mrv.ll index 78d7e776cf..8442d7a7c4 100644 --- a/test/CodeGen/X86/inline-asm-mrv.ll +++ b/test/CodeGen/X86/inline-asm-mrv.ll @@ -1,5 +1,5 @@ ; PR2094 -; RUN: llc < %s -march=x86-64 | grep movslq +; RUN: llc < %s -march=x86-64 | grep movsx ; RUN: llc < %s -march=x86-64 | grep addps ; RUN: llc < %s -march=x86-64 | grep paddd ; RUN: llc < %s -march=x86-64 | not grep movq diff --git a/test/CodeGen/X86/masked-iv-unsafe.ll b/test/CodeGen/X86/masked-iv-unsafe.ll index f23c020195..5698b1a914 100644 --- a/test/CodeGen/X86/masked-iv-unsafe.ll +++ b/test/CodeGen/X86/masked-iv-unsafe.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=x86-64 > %t ; RUN: grep and %t | count 6 -; RUN: grep movzb %t | count 6 +; RUN: grep movzx %t | count 6 ; RUN: grep sar %t | count 12 ; Don't optimize away zext-inreg and sext-inreg on the loop induction diff --git a/test/CodeGen/X86/pr3366.ll b/test/CodeGen/X86/pr3366.ll index 1127b60932..d9c5f53f21 100644 --- a/test/CodeGen/X86/pr3366.ll +++ b/test/CodeGen/X86/pr3366.ll @@ -1,6 +1,7 @@ -; RUN: llc < %s -march=x86 -disable-cgp-branch-opts | grep movzbl +; RUN: llc < %s -march=x86 -disable-cgp-branch-opts | FileCheck %s ; PR3366 +; CHECK: movzx define void @_ada_c34002a() nounwind { entry: %0 = load i8* null, align 1 diff --git a/test/CodeGen/X86/promote-assert-zext.ll b/test/CodeGen/X86/promote-assert-zext.ll index b582806c96..e973c5a466 100644 --- a/test/CodeGen/X86/promote-assert-zext.ll +++ b/test/CodeGen/X86/promote-assert-zext.ll @@ -7,7 +7,7 @@ target triple = "x86_64-apple-darwin11" ; ISel doesn't yet know how to eliminate this extra zero-extend. But until ; it knows how to do so safely, it shouldn;t eliminate it. ; CHECK: movzbl (%rdi), %eax -; CHECK: movzwl %ax, %eax +; CHECK: movzx %ax, %eax define i64 @_ZL5matchPKtPKhiR9MatchData(i8* %tmp13) nounwind { entry: diff --git a/test/CodeGen/X86/promote-i16.ll b/test/CodeGen/X86/promote-i16.ll index 101bb29593..d7622651b1 100644 --- a/test/CodeGen/X86/promote-i16.ll +++ b/test/CodeGen/X86/promote-i16.ll @@ -4,8 +4,8 @@ define signext i16 @foo(i16 signext %x) nounwind { entry: ; CHECK: foo: ; CHECK: movzwl 4(%esp), %eax -; CHECK: xorl $21998, %eax -; CHECK: movswl %ax, %eax +; CHECK: xorl $21998, %eax +; CHECK: movsx %ax, %eax %0 = xor i16 %x, 21998 ret i16 %0 } diff --git a/test/CodeGen/X86/select.ll b/test/CodeGen/X86/select.ll index ce04e07854..02c9502bf9 100644 --- a/test/CodeGen/X86/select.ll +++ b/test/CodeGen/X86/select.ll @@ -30,7 +30,7 @@ bb91: ; preds = %bb84 ret i32 0 ; CHECK: test2: ; CHECK: movnew -; CHECK: movswl +; CHECK: movsx } declare i1 @return_false() diff --git a/test/CodeGen/X86/setcc.ll b/test/CodeGen/X86/setcc.ll index c37e15d24f..349912c6ed 100644 --- a/test/CodeGen/X86/setcc.ll +++ b/test/CodeGen/X86/setcc.ll @@ -8,7 +8,7 @@ define zeroext i16 @t1(i16 zeroext %x) nounwind readnone ssp { entry: ; CHECK: t1: ; CHECK: seta %al -; CHECK: movzbl %al, %eax +; CHECK: movzx %al, %eax ; CHECK: shll $5, %eax %0 = icmp ugt i16 %x, 26 ; [#uses=1] %iftmp.1.0 = select i1 %0, i16 32, i16 0 ; [#uses=1] diff --git a/test/CodeGen/X86/sext-ret-val.ll b/test/CodeGen/X86/sext-ret-val.ll index da1a1871e7..c86e59177f 100644 --- a/test/CodeGen/X86/sext-ret-val.ll +++ b/test/CodeGen/X86/sext-ret-val.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 | grep movzbl | count 1 +; RUN: llc < %s -march=x86 | grep movzx | count 1 ; rdar://6699246 define signext i8 @t1(i8* %A) nounwind readnone ssp { diff --git a/test/CodeGen/X86/sext-subreg.ll b/test/CodeGen/X86/sext-subreg.ll index b2b9f8121f..d6219e09e5 100644 --- a/test/CodeGen/X86/sext-subreg.ll +++ b/test/CodeGen/X86/sext-subreg.ll @@ -3,7 +3,7 @@ define i64 @t(i64 %A, i64 %B, i32* %P, i64 *%P2) nounwind { ; CHECK: t: -; CHECK: movslq %e{{.*}}, %rax +; CHECK: movsx %e{{.*}}, %rax ; CHECK: movq %rax ; CHECK: movl %eax %C = add i64 %A, %B diff --git a/test/CodeGen/X86/shl_elim.ll b/test/CodeGen/X86/shl_elim.ll index 0827221875..d10545cd5d 100644 --- a/test/CodeGen/X86/shl_elim.ll +++ b/test/CodeGen/X86/shl_elim.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=x86 | grep {movl 8(.esp), %eax} ; RUN: llc < %s -march=x86 | grep {shrl .eax} -; RUN: llc < %s -march=x86 | grep {movswl .ax, .eax} +; RUN: llc < %s -march=x86 | grep {movsx .ax, .eax} define i32 @test1(i64 %a) nounwind { %tmp29 = lshr i64 %a, 24 ; [#uses=1] diff --git a/test/CodeGen/X86/umul-with-overflow.ll b/test/CodeGen/X86/umul-with-overflow.ll index c9976617a2..e31ee76905 100644 --- a/test/CodeGen/X86/umul-with-overflow.ll +++ b/test/CodeGen/X86/umul-with-overflow.ll @@ -9,6 +9,6 @@ define i1 @a(i32 %x) zeroext nounwind { ; CHECK: a: ; CHECK: mull ; CHECK: seto %al -; CHECK: movzbl %al, %eax +; CHECK: movzx %al, %eax ; CHECK: ret } diff --git a/test/CodeGen/X86/vshift-4.ll b/test/CodeGen/X86/vshift-4.ll index 8e24fda183..67db3aa0a4 100644 --- a/test/CodeGen/X86/vshift-4.ll +++ b/test/CodeGen/X86/vshift-4.ll @@ -57,7 +57,7 @@ entry: define void @shift3a(<8 x i16> %val, <8 x i16>* %dst, <8 x i16> %amt) nounwind { entry: ; CHECK: shift3a: -; CHECK: movzwl +; CHECK: movzx ; CHECK: psllw %shamt = shufflevector <8 x i16> %amt, <8 x i16> undef, <8 x i32> %shl = shl <8 x i16> %val, %shamt diff --git a/test/CodeGen/X86/widen_conv-2.ll b/test/CodeGen/X86/widen_conv-2.ll index 969cb512be..aa38d9fcb0 100644 --- a/test/CodeGen/X86/widen_conv-2.ll +++ b/test/CodeGen/X86/widen_conv-2.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s -; CHECK: movswl -; CHECK: movswl +; CHECK: movsx +; CHECK: movsx ; sign extension v2i32 to v2i16 diff --git a/test/CodeGen/X86/x86-64-shortint.ll b/test/CodeGen/X86/x86-64-shortint.ll index 7f96543ba4..d610adc633 100644 --- a/test/CodeGen/X86/x86-64-shortint.ll +++ b/test/CodeGen/X86/x86-64-shortint.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s | grep movswl +; RUN: llc < %s | grep movsx target datalayout = "e-p:64:64" target triple = "x86_64-apple-darwin8" diff --git a/test/MC/X86/x86-32.s b/test/MC/X86/x86-32.s index ad9aee5ee5..28900bb7fd 100644 --- a/test/MC/X86/x86-32.s +++ b/test/MC/X86/x86-32.s @@ -613,11 +613,11 @@ pshufw $90, %mm4, %mm0 // CHECK: encoding: [0xd5,0x01] aad $1 -// CHECK: aad $10 +// CHECK: aad // CHECK: encoding: [0xd5,0x0a] aad $0xA -// CHECK: aad $10 +// CHECK: aad // CHECK: encoding: [0xd5,0x0a] aad @@ -625,11 +625,11 @@ pshufw $90, %mm4, %mm0 // CHECK: encoding: [0xd4,0x02] aam $2 -// CHECK: aam $10 +// CHECK: aam // CHECK: encoding: [0xd4,0x0a] aam $0xA -// CHECK: aam $10 +// CHECK: aam // CHECK: encoding: [0xd4,0x0a] aam @@ -725,7 +725,7 @@ pshufw $90, %mm4, %mm0 // CHECK: encoding: [0xdf,0xf2] fcompi %st(2) -// CHECK: fcompi %st(1) +// CHECK: fcompi // CHECK: encoding: [0xdf,0xf1] fcompi @@ -737,7 +737,7 @@ pshufw $90, %mm4, %mm0 // CHECK: encoding: [0xdf,0xea] fucompi %st(2) -// CHECK: fucompi %st(1) +// CHECK: fucompi // CHECK: encoding: [0xdf,0xe9] fucompi @@ -866,9 +866,9 @@ pshufw $90, %mm4, %mm0 movsw %ds:(%esi), %es:(%edi) movsw (%esi), %es:(%edi) -// CHECK: movsl # encoding: [0xa5] -// CHECK: movsl -// CHECK: movsl +// CHECK: movsd # encoding: [0xa5] +// CHECK: movsd +// CHECK: movsd movsl movsl %ds:(%esi), %es:(%edi) movsl (%esi), %es:(%edi) diff --git a/test/MC/X86/x86-64.s b/test/MC/X86/x86-64.s index 80b12dbfc2..55ef050df0 100644 --- a/test/MC/X86/x86-64.s +++ b/test/MC/X86/x86-64.s @@ -112,12 +112,12 @@ // rdar://8470918 smovb // CHECK: movsb smovw // CHECK: movsw -smovl // CHECK: movsl +smovl // CHECK: movsd smovq // CHECK: movsq // rdar://8456361 // CHECK: rep -// CHECK: movsl +// CHECK: movsd rep movsd // CHECK: rep @@ -232,10 +232,10 @@ cmovnzq %rbx, %rax // rdar://8407928 // CHECK: inb $127, %al -// CHECK: inw %dx, %ax +// CHECK: inw %dx // CHECK: outb %al, $127 -// CHECK: outw %ax, %dx -// CHECK: inl %dx, %eax +// CHECK: outw %dx +// CHECK: inl %dx inb $0x7f inw %dx outb $0x7f @@ -244,12 +244,12 @@ inl %dx // PR8114 -// CHECK: outb %al, %dx -// CHECK: outb %al, %dx -// CHECK: outw %ax, %dx -// CHECK: outw %ax, %dx -// CHECK: outl %eax, %dx -// CHECK: outl %eax, %dx +// CHECK: outb %dx +// CHECK: outb %dx +// CHECK: outw %dx +// CHECK: outw %dx +// CHECK: outl %dx +// CHECK: outl %dx out %al, (%dx) outb %al, (%dx) @@ -258,12 +258,12 @@ outw %ax, (%dx) out %eax, (%dx) outl %eax, (%dx) -// CHECK: inb %dx, %al -// CHECK: inb %dx, %al -// CHECK: inw %dx, %ax -// CHECK: inw %dx, %ax -// CHECK: inl %dx, %eax -// CHECK: inl %dx, %eax +// CHECK: inb %dx +// CHECK: inb %dx +// CHECK: inw %dx +// CHECK: inw %dx +// CHECK: inl %dx +// CHECK: inl %dx in (%dx), %al inb (%dx), %al @@ -274,16 +274,16 @@ inl (%dx), %eax // rdar://8431422 -// CHECK: fxch %st(1) -// CHECK: fucom %st(1) -// CHECK: fucomp %st(1) -// CHECK: faddp %st(1) +// CHECK: fxch +// CHECK: fucom +// CHECK: fucomp +// CHECK: faddp // CHECK: faddp %st(0) -// CHECK: fsubp %st(1) -// CHECK: fsubrp %st(1) -// CHECK: fmulp %st(1) -// CHECK: fdivp %st(1) -// CHECK: fdivrp %st(1) +// CHECK: fsubp +// CHECK: fsubrp +// CHECK: fmulp +// CHECK: fdivp +// CHECK: fdivrp fxch fucom @@ -296,11 +296,11 @@ fmulp fdivp fdivrp -// CHECK: fcomi %st(1) +// CHECK: fcomi // CHECK: fcomi %st(2) -// CHECK: fucomi %st(1) -// CHECK: fucomi %st(2) -// CHECK: fucomi %st(2) +// CHECK: fucomi +// CHECK: fucomi %st(2) +// CHECK: fucomi %st(2) fcomi fcomi %st(2) @@ -604,7 +604,7 @@ movsq // CHECK: encoding: [0x48,0xa5] movsl -// CHECK: movsl +// CHECK: movsd // CHECK: encoding: [0xa5] stosq @@ -681,65 +681,65 @@ btq $0x01,%rdx // CHECK: encoding: [0x48,0x0f,0xba,0xe2,0x01] //rdar://8017633 -// CHECK: movzbl %al, %esi +// CHECK: movzx %al, %esi // CHECK: encoding: [0x0f,0xb6,0xf0] movzx %al, %esi -// CHECK: movzbq %al, %rsi +// CHECK: movzx %al, %rsi // CHECK: encoding: [0x48,0x0f,0xb6,0xf0] movzx %al, %rsi -// CHECK: movsbw %al, %ax +// CHECK: movsx %al, %ax // CHECK: encoding: [0x66,0x0f,0xbe,0xc0] -movsx %al, %ax + movsx %al, %ax -// CHECK: movsbl %al, %eax +// CHECK: movsx %al, %eax // CHECK: encoding: [0x0f,0xbe,0xc0] -movsx %al, %eax + movsx %al, %eax -// CHECK: movswl %ax, %eax +// CHECK: movsx %ax, %eax // CHECK: encoding: [0x0f,0xbf,0xc0] -movsx %ax, %eax + movsx %ax, %eax -// CHECK: movsbq %bl, %rax +// CHECK: movsx %bl, %rax // CHECK: encoding: [0x48,0x0f,0xbe,0xc3] -movsx %bl, %rax + movsx %bl, %rax -// CHECK: movswq %cx, %rax +// CHECK: movsx %cx, %rax // CHECK: encoding: [0x48,0x0f,0xbf,0xc1] -movsx %cx, %rax + movsx %cx, %rax -// CHECK: movslq %edi, %rax +// CHECK: movsx %edi, %rax // CHECK: encoding: [0x48,0x63,0xc7] -movsx %edi, %rax + movsx %edi, %rax -// CHECK: movzbw %al, %ax +// CHECK: movzx %al, %ax // CHECK: encoding: [0x66,0x0f,0xb6,0xc0] -movzx %al, %ax + movzx %al, %ax -// CHECK: movzbl %al, %eax +// CHECK: movzx %al, %eax // CHECK: encoding: [0x0f,0xb6,0xc0] -movzx %al, %eax + movzx %al, %eax -// CHECK: movzwl %ax, %eax +// CHECK: movzx %ax, %eax // CHECK: encoding: [0x0f,0xb7,0xc0] -movzx %ax, %eax + movzx %ax, %eax -// CHECK: movzbq %bl, %rax +// CHECK: movzx %bl, %rax // CHECK: encoding: [0x48,0x0f,0xb6,0xc3] -movzx %bl, %rax + movzx %bl, %rax -// CHECK: movzwq %cx, %rax +// CHECK: movzx %cx, %rax // CHECK: encoding: [0x48,0x0f,0xb7,0xc1] -movzx %cx, %rax + movzx %cx, %rax // CHECK: movsbw (%rax), %ax // CHECK: encoding: [0x66,0x0f,0xbe,0x00] -movsx (%rax), %ax + movsx (%rax), %ax // CHECK: movzbw (%rax), %ax // CHECK: encoding: [0x66,0x0f,0xb6,0x00] -movzx (%rax), %ax + movzx (%rax), %ax // rdar://7873482 @@ -790,7 +790,7 @@ lock/incl 1(%rsp) rep movsl // CHECK: rep // CHECK: encoding: [0xf3] -// CHECK: movsl +// CHECK: movsd // CHECK: encoding: [0xa5] @@ -1027,9 +1027,9 @@ xsetbv // CHECK: xsetbv # encoding: [0x0f,0x01,0xd1] movsw %ds:(%rsi), %es:(%rdi) movsw (%rsi), %es:(%rdi) -// CHECK: movsl # encoding: [0xa5] -// CHECK: movsl -// CHECK: movsl +// CHECK: movsd # encoding: [0xa5] +// CHECK: movsd +// CHECK: movsd movsl movsl %ds:(%rsi), %es:(%rdi) movsl (%rsi), %es:(%rdi) -- cgit v1.2.3