From f89f66e61b26974bb73b5832d5825091873b51dc Mon Sep 17 00:00:00 2001 From: Matheus Almeida Date: Mon, 21 Oct 2013 11:47:56 +0000 Subject: [mips][msa] Fix definition of SLD instruction. The second parameter of the SLD intrinsic is the number of columns (GPR) to slide left the source array. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193076 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/Mips/msa/3r-s.ll | 54 +++++++++++++++++++++---------------------- test/MC/Mips/msa/test_3r.s | 24 +++++++++---------- 2 files changed, 39 insertions(+), 39 deletions(-) (limited to 'test') diff --git a/test/CodeGen/Mips/msa/3r-s.ll b/test/CodeGen/Mips/msa/3r-s.ll index 360bd4cfb2..1b894cf5a4 100644 --- a/test/CodeGen/Mips/msa/3r-s.ll +++ b/test/CodeGen/Mips/msa/3r-s.ll @@ -4,98 +4,98 @@ ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s @llvm_mips_sld_b_ARG1 = global <16 x i8> , align 16 -@llvm_mips_sld_b_ARG2 = global <16 x i8> , align 16 +@llvm_mips_sld_b_ARG2 = global i32 10, align 16 @llvm_mips_sld_b_RES = global <16 x i8> , align 16 define void @llvm_mips_sld_b_test() nounwind { entry: %0 = load <16 x i8>* @llvm_mips_sld_b_ARG1 - %1 = load <16 x i8>* @llvm_mips_sld_b_ARG2 - %2 = tail call <16 x i8> @llvm.mips.sld.b(<16 x i8> %0, <16 x i8> %1) + %1 = load i32* @llvm_mips_sld_b_ARG2 + %2 = tail call <16 x i8> @llvm.mips.sld.b(<16 x i8> %0, i32 %1) store <16 x i8> %2, <16 x i8>* @llvm_mips_sld_b_RES ret void } -declare <16 x i8> @llvm.mips.sld.b(<16 x i8>, <16 x i8>) nounwind +declare <16 x i8> @llvm.mips.sld.b(<16 x i8>, i32) nounwind ; CHECK: llvm_mips_sld_b_test: ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sld_b_ARG1) ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sld_b_ARG2) ; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]]) -; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]]) -; CHECK-DAG: sld.b [[WD:\$w[0-9]+]], [[WS]], [[WT]] +; CHECK-DAG: lw [[RT:\$[0-9]+]], 0([[R2]]) +; CHECK-DAG: sld.b [[WD:\$w[0-9]+]], [[WS]]{{\[}}[[RT]]{{\]}} ; CHECK-DAG: st.b [[WD]] ; CHECK: .size llvm_mips_sld_b_test ; @llvm_mips_sld_h_ARG1 = global <8 x i16> , align 16 -@llvm_mips_sld_h_ARG2 = global <8 x i16> , align 16 +@llvm_mips_sld_h_ARG2 = global i32 10, align 16 @llvm_mips_sld_h_RES = global <8 x i16> , align 16 define void @llvm_mips_sld_h_test() nounwind { entry: %0 = load <8 x i16>* @llvm_mips_sld_h_ARG1 - %1 = load <8 x i16>* @llvm_mips_sld_h_ARG2 - %2 = tail call <8 x i16> @llvm.mips.sld.h(<8 x i16> %0, <8 x i16> %1) + %1 = load i32* @llvm_mips_sld_h_ARG2 + %2 = tail call <8 x i16> @llvm.mips.sld.h(<8 x i16> %0, i32 %1) store <8 x i16> %2, <8 x i16>* @llvm_mips_sld_h_RES ret void } -declare <8 x i16> @llvm.mips.sld.h(<8 x i16>, <8 x i16>) nounwind +declare <8 x i16> @llvm.mips.sld.h(<8 x i16>, i32) nounwind ; CHECK: llvm_mips_sld_h_test: ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sld_h_ARG1) -; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sld_h_ARG2) +; CHECK-DAG: lw [[RT:\$[0-9]+]], %got(llvm_mips_sld_h_ARG2) ; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]]) -; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]]) -; CHECK-DAG: sld.h [[WD:\$w[0-9]+]], [[WS]], [[WT]] +; CHECK-DAG: lw [[RT:\$[0-9]+]], 0([[R2]]) +; CHECK-DAG: sld.h [[WD:\$w[0-9]+]], [[WS]]{{\[}}[[RT]]{{\]}} ; CHECK-DAG: st.h [[WD]] ; CHECK: .size llvm_mips_sld_h_test ; @llvm_mips_sld_w_ARG1 = global <4 x i32> , align 16 -@llvm_mips_sld_w_ARG2 = global <4 x i32> , align 16 +@llvm_mips_sld_w_ARG2 = global i32 10, align 16 @llvm_mips_sld_w_RES = global <4 x i32> , align 16 define void @llvm_mips_sld_w_test() nounwind { entry: %0 = load <4 x i32>* @llvm_mips_sld_w_ARG1 - %1 = load <4 x i32>* @llvm_mips_sld_w_ARG2 - %2 = tail call <4 x i32> @llvm.mips.sld.w(<4 x i32> %0, <4 x i32> %1) + %1 = load i32* @llvm_mips_sld_w_ARG2 + %2 = tail call <4 x i32> @llvm.mips.sld.w(<4 x i32> %0, i32 %1) store <4 x i32> %2, <4 x i32>* @llvm_mips_sld_w_RES ret void } -declare <4 x i32> @llvm.mips.sld.w(<4 x i32>, <4 x i32>) nounwind +declare <4 x i32> @llvm.mips.sld.w(<4 x i32>, i32) nounwind ; CHECK: llvm_mips_sld_w_test: ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sld_w_ARG1) -; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sld_w_ARG2) +; CHECK-DAG: lw [[RT:\$[0-9]+]], %got(llvm_mips_sld_w_ARG2) ; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]]) -; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]]) -; CHECK-DAG: sld.w [[WD:\$w[0-9]+]], [[WS]], [[WT]] +; CHECK-DAG: lw [[RT:\$[0-9]+]], 0([[R2]]) +; CHECK-DAG: sld.w [[WD:\$w[0-9]+]], [[WS]]{{\[}}[[RT]]{{\]}} ; CHECK-DAG: st.w [[WD]] ; CHECK: .size llvm_mips_sld_w_test ; @llvm_mips_sld_d_ARG1 = global <2 x i64> , align 16 -@llvm_mips_sld_d_ARG2 = global <2 x i64> , align 16 +@llvm_mips_sld_d_ARG2 = global i32 10, align 16 @llvm_mips_sld_d_RES = global <2 x i64> , align 16 define void @llvm_mips_sld_d_test() nounwind { entry: %0 = load <2 x i64>* @llvm_mips_sld_d_ARG1 - %1 = load <2 x i64>* @llvm_mips_sld_d_ARG2 - %2 = tail call <2 x i64> @llvm.mips.sld.d(<2 x i64> %0, <2 x i64> %1) + %1 = load i32* @llvm_mips_sld_d_ARG2 + %2 = tail call <2 x i64> @llvm.mips.sld.d(<2 x i64> %0, i32 %1) store <2 x i64> %2, <2 x i64>* @llvm_mips_sld_d_RES ret void } -declare <2 x i64> @llvm.mips.sld.d(<2 x i64>, <2 x i64>) nounwind +declare <2 x i64> @llvm.mips.sld.d(<2 x i64>, i32) nounwind ; CHECK: llvm_mips_sld_d_test: ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sld_d_ARG1) -; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sld_d_ARG2) +; CHECK-DAG: lw [[RT:\$[0-9]+]], %got(llvm_mips_sld_d_ARG2) ; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]]) -; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]]) -; CHECK-DAG: sld.d [[WD:\$w[0-9]+]], [[WS]], [[WT]] +; CHECK-DAG: lw [[RT:\$[0-9]+]], 0([[R2]]) +; CHECK-DAG: sld.d [[WD:\$w[0-9]+]], [[WS]]{{\[}}[[RT]]{{\]}} ; CHECK-DAG: st.d [[WD]] ; CHECK: .size llvm_mips_sld_d_test ; diff --git a/test/MC/Mips/msa/test_3r.s b/test/MC/Mips/msa/test_3r.s index 6a10bd53be..be7e9fb435 100644 --- a/test/MC/Mips/msa/test_3r.s +++ b/test/MC/Mips/msa/test_3r.s @@ -192,10 +192,10 @@ # CHECK: pckod.h $w26, $w5, $w8 # encoding: [0x79,0xa8,0x2e,0x94] # CHECK: pckod.w $w9, $w4, $w2 # encoding: [0x79,0xc2,0x22,0x54] # CHECK: pckod.d $w30, $w22, $w20 # encoding: [0x79,0xf4,0xb7,0x94] -# CHECK: sld.b $w5, $w23, $w12 # encoding: [0x78,0x0c,0xb9,0x54] -# CHECK: sld.h $w1, $w23, $w3 # encoding: [0x78,0x23,0xb8,0x54] -# CHECK: sld.w $w20, $w8, $w9 # encoding: [0x78,0x49,0x45,0x14] -# CHECK: sld.d $w7, $w23, $w30 # encoding: [0x78,0x7e,0xb9,0xd4] +# CHECK: sld.b $w5, $w23[$12] # encoding: [0x78,0x0c,0xb9,0x54] +# CHECK: sld.h $w1, $w23[$3] # encoding: [0x78,0x23,0xb8,0x54] +# CHECK: sld.w $w20, $w8[$9] # encoding: [0x78,0x49,0x45,0x14] +# CHECK: sld.d $w7, $w23[$fp] # encoding: [0x78,0x7e,0xb9,0xd4] # CHECK: sll.b $w3, $w0, $w17 # encoding: [0x78,0x11,0x00,0xcd] # CHECK: sll.h $w17, $w27, $w3 # encoding: [0x78,0x23,0xdc,0x4d] # CHECK: sll.w $w16, $w7, $w6 # encoding: [0x78,0x46,0x3c,0x0d] @@ -431,10 +431,10 @@ # CHECKOBJDUMP: pckod.h $w26, $w5, $w8 # CHECKOBJDUMP: pckod.w $w9, $w4, $w2 # CHECKOBJDUMP: pckod.d $w30, $w22, $w20 -# CHECKOBJDUMP: sld.b $w5, $w23, $w12 -# CHECKOBJDUMP: sld.h $w1, $w23, $w3 -# CHECKOBJDUMP: sld.w $w20, $w8, $w9 -# CHECKOBJDUMP: sld.d $w7, $w23, $w30 +# CHECKOBJDUMP: sld.b $w5, $w23[$12] +# CHECKOBJDUMP: sld.h $w1, $w23[$3] +# CHECKOBJDUMP: sld.w $w20, $w8[$9] +# CHECKOBJDUMP: sld.d $w7, $w23[$fp] # CHECKOBJDUMP: sll.b $w3, $w0, $w17 # CHECKOBJDUMP: sll.h $w17, $w27, $w3 # CHECKOBJDUMP: sll.w $w16, $w7, $w6 @@ -670,10 +670,10 @@ pckod.h $w26, $w5, $w8 pckod.w $w9, $w4, $w2 pckod.d $w30, $w22, $w20 - sld.b $w5, $w23, $w12 - sld.h $w1, $w23, $w3 - sld.w $w20, $w8, $w9 - sld.d $w7, $w23, $w30 + sld.b $w5, $w23[$12] + sld.h $w1, $w23[$3] + sld.w $w20, $w8[$9] + sld.d $w7, $w23[$30] sll.b $w3, $w0, $w17 sll.h $w17, $w27, $w3 sll.w $w16, $w7, $w6 -- cgit v1.2.3