From 53452606ca04929257b3bcbfa5e0d59a44925882 Mon Sep 17 00:00:00 2001 From: Eric Christopher Date: Wed, 25 Aug 2010 04:58:56 +0000 Subject: Allow strict subclasses of register classes, this way we can handle ARM instructions with: foo GPR, rGPR which happens a lot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112025 91177308-0d34-0410-b5e6-96231b3b80d8 --- utils/TableGen/FastISelEmitter.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'utils/TableGen/FastISelEmitter.cpp') diff --git a/utils/TableGen/FastISelEmitter.cpp b/utils/TableGen/FastISelEmitter.cpp index 243208612d..6c16fcfaa8 100644 --- a/utils/TableGen/FastISelEmitter.cpp +++ b/utils/TableGen/FastISelEmitter.cpp @@ -112,9 +112,10 @@ struct OperandsSignature { if (!RC) return false; - // For now, all the operands must have the same register class. + // For now, all the operands must have the same register class or be + // a strict subclass of the destination. if (DstRC) { - if (DstRC != RC) + if (DstRC != RC && !DstRC->hasSubClass(RC)) return false; } else DstRC = RC; -- cgit v1.2.3