From dd63a063e2df0d0bc52b50732e3462fd58a636c0 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Thu, 3 May 2012 22:49:04 +0000 Subject: Use a shared implementation of getMatchingSuperRegClass(). TargetRegisterClass now gives access to the necessary tables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156122 91177308-0d34-0410-b5e6-96231b3b80d8 --- utils/TableGen/RegisterInfoEmitter.cpp | 35 +--------------------------------- 1 file changed, 1 insertion(+), 34 deletions(-) (limited to 'utils/TableGen/RegisterInfoEmitter.cpp') diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp index 6769892db4..6c21032233 100644 --- a/utils/TableGen/RegisterInfoEmitter.cpp +++ b/utils/TableGen/RegisterInfoEmitter.cpp @@ -680,10 +680,7 @@ RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target, if (!RegBank.getSubRegIndices().empty()) { OS << " unsigned composeSubRegIndices(unsigned, unsigned) const;\n" << " const TargetRegisterClass *" - "getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const;\n" - << " const TargetRegisterClass *getMatchingSuperRegClass(" - "const TargetRegisterClass*, const TargetRegisterClass*, " - "unsigned) const;\n"; + "getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const;\n"; } OS << " const RegClassWeight &getRegClassWeight(" << "const TargetRegisterClass *RC) const;\n" @@ -734,9 +731,6 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, ArrayRef RegisterClasses = RegBank.getRegClasses(); ArrayRef SubRegIndices = RegBank.getSubRegIndices(); - // The number of 32-bit words in a register class bit mask. - const unsigned RCMaskWords = (RegisterClasses.size()+31)/32; - // Collect all registers belonging to any allocatable class. std::set AllocatableRegs; @@ -1050,33 +1044,6 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, << " return TV ? getRegClass(TV - 1) : 0;\n}\n\n"; } - if (!SubRegIndices.empty()) { - // Emit getMatchingSuperRegClass. - // We need to find the largest sub-class of A such that every register has - // an Idx sub-register in B. Map (B, Idx) to a bit-vector of - // super-register classes that map into B. Then compute the largest common - // sub-class with A by taking advantage of the register class ordering, - // like getCommonSubClass(). - OS << "const TargetRegisterClass *" << ClassName - << "::getMatchingSuperRegClass(const TargetRegisterClass *A," - << " const TargetRegisterClass *B, unsigned Idx) const {\n" - << " assert(A && B && \"Missing regclass\");\n" - << " assert(Idx && Idx <= " << SubRegIndices.size() - << " && \"Bad subreg\");\n" - << " const uint16_t *SRI = B->getSuperRegIndices();\n" - << " unsigned Offset = 0;\n" - << " while (SRI[Offset] != Idx) {\n" - << " if (!SRI[Offset])\n return 0;\n" - << " ++Offset;\n }\n" - << " const uint32_t *TV = B->getSubClassMask() + (Offset+1)*" - << RCMaskWords << ";\n" - << " const uint32_t *SC = A->getSubClassMask();\n" - << " for (unsigned i = 0; i != " << RCMaskWords << "; ++i)\n" - << " if (unsigned Common = TV[i] & SC[i])\n" - << " return getRegClass(32*i + CountTrailingZeros_32(Common));\n" - << " return 0;\n}\n\n"; - } - EmitRegUnitPressure(OS, RegBank, ClassName); // Emit the constructor of the class... -- cgit v1.2.3