From 169e66bfc23c20a3df7d0364f5f1abb43f33694b Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Sun, 3 Aug 2003 17:24:20 +0000 Subject: Add support for instruction enum emission git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7516 91177308-0d34-0410-b5e6-96231b3b80d8 --- utils/TableGen/TableGen.cpp | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'utils/TableGen/TableGen.cpp') diff --git a/utils/TableGen/TableGen.cpp b/utils/TableGen/TableGen.cpp index 1d8b60bed3..990e2b3b35 100644 --- a/utils/TableGen/TableGen.cpp +++ b/utils/TableGen/TableGen.cpp @@ -14,6 +14,7 @@ #include "Support/FileUtilities.h" #include "CodeEmitterGen.h" #include "RegisterInfoEmitter.h" +#include "InstrInfoEmitter.h" #include #include @@ -21,6 +22,7 @@ enum ActionType { PrintRecords, GenEmitter, GenRegisterEnums, GenRegister, GenRegisterHeader, + GenInstrEnums, PrintEnums, Parse, }; @@ -38,6 +40,8 @@ namespace { "Generate a register info description"), clEnumValN(GenRegisterHeader, "gen-register-desc-header", "Generate a register info description header"), + clEnumValN(GenInstrEnums, "gen-instr-enums", + "Generate enum values for instructions"), clEnumValN(PrintEnums, "print-enums", "Print enum values for a class"), clEnumValN(Parse, "parse", @@ -417,6 +421,7 @@ int main(int argc, char **argv) { case GenEmitter: CodeEmitterGen(Records).run(*Out); break; + case GenRegisterEnums: RegisterInfoEmitter(Records).runEnums(*Out); break; @@ -426,6 +431,11 @@ int main(int argc, char **argv) { case GenRegisterHeader: RegisterInfoEmitter(Records).runHeader(*Out); break; + + case GenInstrEnums: + InstrInfoEmitter(Records).runEnums(*Out); + break; + case PrintEnums: std::vector Recs = Records.getAllDerivedDefinitions(Class); for (unsigned i = 0, e = Recs.size(); i != e; ++i) -- cgit v1.2.3