From 7c3e057ff49a67814a48a2702d56faf2a624f9a6 Mon Sep 17 00:00:00 2001 From: Tim Northover Date: Sat, 29 Mar 2014 07:04:54 +0000 Subject: Intrinsics: add LLVMHalfElementsVectorType constraint This is like the LLVMMatchType, except the verifier checks that the second argument is a vector with the same base type and half the number of elements. This will be used by the ARM64 backend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205079 91177308-0d34-0410-b5e6-96231b3b80d8 --- utils/TableGen/IntrinsicEmitter.cpp | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'utils/TableGen') diff --git a/utils/TableGen/IntrinsicEmitter.cpp b/utils/TableGen/IntrinsicEmitter.cpp index dc32dfa858..7b0a2b6c6d 100644 --- a/utils/TableGen/IntrinsicEmitter.cpp +++ b/utils/TableGen/IntrinsicEmitter.cpp @@ -250,7 +250,8 @@ enum IIT_Info { IIT_TRUNC_ARG = 24, IIT_ANYPTR = 25, IIT_V1 = 26, - IIT_VARARG = 27 + IIT_VARARG = 27, + IIT_HALF_VEC_ARG = 28 }; @@ -296,6 +297,8 @@ static void EncodeFixedType(Record *R, std::vector &ArgCodes, Sig.push_back(IIT_EXTEND_ARG); else if (R->isSubClassOf("LLVMTruncatedType")) Sig.push_back(IIT_TRUNC_ARG); + else if (R->isSubClassOf("LLVMHalfElementsVectorType")) + Sig.push_back(IIT_HALF_VEC_ARG); else Sig.push_back(IIT_ARG); return Sig.push_back((Number << 2) | ArgCodes[Number]); -- cgit v1.2.3