From be5d6bcfc6ad4d5b771bb491c8ec6c87fcd3c425 Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Fri, 28 Oct 2011 16:43:40 +0000 Subject: Allow register classes to match a containing class in InstAliases. If the register class in the source alias is a subclass of the register class of the actual instruction, the alias can still match OK since the constraints are strictly a subset of what the instruction can actually handle. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143200 91177308-0d34-0410-b5e6-96231b3b80d8 --- utils/TableGen/CodeGenInstruction.cpp | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'utils/TableGen') diff --git a/utils/TableGen/CodeGenInstruction.cpp b/utils/TableGen/CodeGenInstruction.cpp index 53d499f395..9822de819d 100644 --- a/utils/TableGen/CodeGenInstruction.cpp +++ b/utils/TableGen/CodeGenInstruction.cpp @@ -423,6 +423,15 @@ bool CodeGenInstAlias::tryAliasOpMatch(DagInit *Result, unsigned AliasOpNo, return true; } + // For register operands, the source register class can be a subclass + // of the instruction register class, not just an exact match. + if (ADI && ADI->getDef()->isSubClassOf("RegisterClass")) { + if (!InstOpRec->isSubClassOf("RegisterClass")) + return false; + return T.getRegisterClass(InstOpRec) + .hasSubClass(&T.getRegisterClass(ADI->getDef())); + } + // Handle explicit registers. if (ADI && ADI->getDef()->isSubClassOf("Register")) { if (InstOpRec->isSubClassOf("OptionalDefOperand")) { -- cgit v1.2.3