From 828295bb301d6cd3683751c2da1c2dd22ec6423f Mon Sep 17 00:00:00 2001 From: Bob Wilson Date: Wed, 26 Jan 2011 21:26:19 +0000 Subject: Whitespace and 80-column fixes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124323 91177308-0d34-0410-b5e6-96231b3b80d8 --- utils/TableGen/AsmMatcherEmitter.cpp | 228 +++++++++++++++++------------------ 1 file changed, 109 insertions(+), 119 deletions(-) (limited to 'utils') diff --git a/utils/TableGen/AsmMatcherEmitter.cpp b/utils/TableGen/AsmMatcherEmitter.cpp index aa8cc4e4c7..109f6bd9bd 100644 --- a/utils/TableGen/AsmMatcherEmitter.cpp +++ b/utils/TableGen/AsmMatcherEmitter.cpp @@ -90,9 +90,8 @@ static cl::opt MatchPrefix("match-prefix", cl::init(""), cl::desc("Only match instructions with the given prefix")); - namespace { - class AsmMatcherInfo; +class AsmMatcherInfo; struct SubtargetFeatureInfo; /// ClassInfo - Helper class for storing the information about a particular @@ -247,7 +246,7 @@ struct MatchableInfo { struct AsmOperand { /// Token - This is the token that the operand came from. StringRef Token; - + /// The unique class instance this operand should match. ClassInfo *Class; @@ -256,10 +255,10 @@ struct MatchableInfo { /// The suboperand index within SrcOpName, or -1 for the entire operand. int SubOpIdx; - + explicit AsmOperand(StringRef T) : Token(T), Class(0), SubOpIdx(-1) {} }; - + /// ResOperand - This represents a single operand in the result instruction /// generated by the match. In cases (like addressing modes) where a single /// assembler operand expands to multiple MCOperands, this represents the @@ -270,39 +269,39 @@ struct MatchableInfo { /// generated by calling the render method on the assembly operand. The /// corresponding AsmOperand is specified by AsmOperandNum. RenderAsmOperand, - + /// TiedOperand - This represents a result operand that is a duplicate of /// a previous result operand. TiedOperand, - + /// ImmOperand - This represents an immediate value that is dumped into /// the operand. ImmOperand, - + /// RegOperand - This represents a fixed register that is dumped in. RegOperand } Kind; - + union { /// This is the operand # in the AsmOperands list that this should be /// copied from. unsigned AsmOperandNum; - + /// TiedOperandNum - This is the (earlier) result operand that should be /// copied from. unsigned TiedOperandNum; - + /// ImmVal - This is the immediate value added to the instruction. int64_t ImmVal; - + /// Register - This is the register record. Record *Register; }; - + /// MINumOperands - The number of MCInst operands populated by this /// operand. unsigned MINumOperands; - + static ResOperand getRenderedOp(unsigned AsmOpNum, unsigned NumOperands) { ResOperand X; X.Kind = RenderAsmOperand; @@ -310,7 +309,7 @@ struct MatchableInfo { X.MINumOperands = NumOperands; return X; } - + static ResOperand getTiedOp(unsigned TiedOperandNum) { ResOperand X; X.Kind = TiedOperand; @@ -318,7 +317,7 @@ struct MatchableInfo { X.MINumOperands = 1; return X; } - + static ResOperand getImmOp(int64_t Val) { ResOperand X; X.Kind = ImmOperand; @@ -326,7 +325,7 @@ struct MatchableInfo { X.MINumOperands = 1; return X; } - + static ResOperand getRegOp(Record *Reg) { ResOperand X; X.Kind = RegOperand; @@ -339,16 +338,16 @@ struct MatchableInfo { /// TheDef - This is the definition of the instruction or InstAlias that this /// matchable came from. Record *const TheDef; - + /// DefRec - This is the definition that it came from. PointerUnion DefRec; - + const CodeGenInstruction *getResultInst() const { if (DefRec.is()) return DefRec.get(); return DefRec.get()->ResultInst; } - + /// ResOperands - This is the operand list that should be built for the result /// MCInst. std::vector ResOperands; @@ -360,7 +359,7 @@ struct MatchableInfo { /// Mnemonic - This is the first token of the matched instruction, its /// mnemonic. StringRef Mnemonic; - + /// AsmOperands - The textual operands that this instruction matches, /// annotated with a class and where in the OperandList they were defined. /// This directly corresponds to the tokenized AsmString after the mnemonic is @@ -374,7 +373,7 @@ struct MatchableInfo { /// ConvertToMCInst to convert parsed operands into an MCInst for this /// function. std::string ConversionFnKind; - + MatchableInfo(const CodeGenInstruction &CGI) : TheDef(CGI.TheDef), DefRec(&CGI), AsmString(CGI.AsmString) { } @@ -382,18 +381,18 @@ struct MatchableInfo { MatchableInfo(const CodeGenInstAlias *Alias) : TheDef(Alias->TheDef), DefRec(Alias), AsmString(Alias->AsmString) { } - + void Initialize(const AsmMatcherInfo &Info, SmallPtrSet &SingletonRegisters); - + /// Validate - Return true if this matchable is a valid thing to match against /// and perform a bunch of validity checking. bool Validate(StringRef CommentDelimiter, bool Hack) const; - + /// getSingletonRegisterForAsmOperand - If the specified token is a singleton /// register, return the Record for it, otherwise return null. Record *getSingletonRegisterForAsmOperand(unsigned i, - const AsmMatcherInfo &Info) const; + const AsmMatcherInfo &Info) const; /// FindAsmOperand - Find the AsmOperand with the specified name and /// suboperand index. @@ -404,7 +403,7 @@ struct MatchableInfo { return i; return -1; } - + /// FindAsmOperandNamed - Find the first AsmOperand with the specified name. /// This does not check the suboperand index. int FindAsmOperandNamed(StringRef N) const { @@ -413,7 +412,7 @@ struct MatchableInfo { return i; return -1; } - + void BuildInstructionResultOperands(); void BuildAliasResultOperands(); @@ -445,7 +444,7 @@ struct MatchableInfo { // The primary comparator is the instruction mnemonic. if (Mnemonic != RHS.Mnemonic) return false; - + // The number of operands is unambiguous. if (AsmOperands.size() != RHS.AsmOperands.size()) return false; @@ -478,7 +477,7 @@ struct MatchableInfo { } void dump(); - + private: void TokenizeAsmString(const AsmMatcherInfo &Info); }; @@ -493,7 +492,7 @@ struct SubtargetFeatureInfo { unsigned Index; SubtargetFeatureInfo(Record *D, unsigned Idx) : TheDef(D), Index(Idx) {} - + /// \brief The name of the enumerated constant identifying this feature. std::string getEnumName() const { return "Feature_" + TheDef->getName(); @@ -525,7 +524,7 @@ public: /// Map of Predicate records to their subtarget information. std::map SubtargetFeatures; - + private: /// Map of token to class information which has already been constructed. std::map TokenClasses; @@ -556,15 +555,15 @@ private: unsigned AsmOpIdx); void BuildAliasOperandReference(MatchableInfo *II, StringRef OpName, MatchableInfo::AsmOperand &Op); - + public: - AsmMatcherInfo(Record *AsmParser, - CodeGenTarget &Target, + AsmMatcherInfo(Record *AsmParser, + CodeGenTarget &Target, RecordKeeper &Records); /// BuildInfo - Construct the various tables used during matching. void BuildInfo(); - + /// getSubtargetFeature - Lookup or create the subtarget feature info for the /// given operand. SubtargetFeatureInfo *getSubtargetFeature(Record *Def) const { @@ -595,16 +594,16 @@ void MatchableInfo::Initialize(const AsmMatcherInfo &Info, SmallPtrSet &SingletonRegisters) { // TODO: Eventually support asmparser for Variant != 0. AsmString = CodeGenInstruction::FlattenAsmStringVariants(AsmString, 0); - + TokenizeAsmString(Info); - + // Compute the require features. std::vector Predicates =TheDef->getValueAsListOfDefs("Predicates"); for (unsigned i = 0, e = Predicates.size(); i != e; ++i) if (SubtargetFeatureInfo *Feature = Info.getSubtargetFeature(Predicates[i])) RequiredFeatures.push_back(Feature); - + // Collect singleton registers, if used. for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) { if (Record *Reg = getSingletonRegisterForAsmOperand(i, Info)) @@ -651,7 +650,7 @@ void MatchableInfo::TokenizeAsmString(const AsmMatcherInfo &Info) { AsmOperands.push_back(AsmOperand(String.slice(Prev, i))); InTok = false; } - + // If this isn't "${", treat like a normal token. if (i + 1 == String.size() || String[i + 1] != '{') { Prev = i; @@ -680,7 +679,7 @@ void MatchableInfo::TokenizeAsmString(const AsmMatcherInfo &Info) { } if (InTok && Prev != String.size()) AsmOperands.push_back(AsmOperand(String.substr(Prev))); - + // The first token of the instruction is the mnemonic, which must be a // simple string, not a $foo variable or a singleton register. assert(!AsmOperands.empty() && "Instruction has no tokens?"); @@ -688,25 +687,23 @@ void MatchableInfo::TokenizeAsmString(const AsmMatcherInfo &Info) { if (Mnemonic[0] == '$' || getSingletonRegisterForAsmOperand(0, Info)) throw TGError(TheDef->getLoc(), "Invalid instruction mnemonic '" + Mnemonic.str() + "'!"); - + // Remove the first operand, it is tracked in the mnemonic field. AsmOperands.erase(AsmOperands.begin()); } - - bool MatchableInfo::Validate(StringRef CommentDelimiter, bool Hack) const { // Reject matchables with no .s string. if (AsmString.empty()) throw TGError(TheDef->getLoc(), "instruction with empty asm string"); - + // Reject any matchables with a newline in them, they should be marked // isCodeGenOnly if they are pseudo instructions. if (AsmString.find('\n') != std::string::npos) throw TGError(TheDef->getLoc(), "multiline instruction is not valid for the asmparser, " "mark it isCodeGenOnly"); - + // Remove comments from the asm string. We know that the asmstring only // has one line. if (!CommentDelimiter.empty() && @@ -714,7 +711,7 @@ bool MatchableInfo::Validate(StringRef CommentDelimiter, bool Hack) const { throw TGError(TheDef->getLoc(), "asmstring for instruction has comment character in it, " "mark it isCodeGenOnly"); - + // Reject matchables with operand modifiers, these aren't something we can // handle, the target should be refactored to use operands instead of // modifiers. @@ -728,7 +725,7 @@ bool MatchableInfo::Validate(StringRef CommentDelimiter, bool Hack) const { throw TGError(TheDef->getLoc(), "matchable with operand modifier '" + Tok.str() + "' not supported by asm matcher. Mark isCodeGenOnly!"); - + // Verify that any operand is only mentioned once. // We reject aliases and ignore instructions for now. if (Tok[0] == '$' && !OperandNames.insert(Tok).second) { @@ -746,11 +743,10 @@ bool MatchableInfo::Validate(StringRef CommentDelimiter, bool Hack) const { return false; } } - + return true; } - /// getSingletonRegisterForAsmOperand - If the specified token is a singleton /// register, return the register name, otherwise return a null StringRef. Record *MatchableInfo:: @@ -758,16 +754,16 @@ getSingletonRegisterForAsmOperand(unsigned i, const AsmMatcherInfo &Info) const{ StringRef Tok = AsmOperands[i].Token; if (!Tok.startswith(Info.RegisterPrefix)) return 0; - + StringRef RegName = Tok.substr(Info.RegisterPrefix.size()); if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(RegName)) return Reg->TheDef; - + // If there is no register prefix (i.e. "%" in "%eax"), then this may // be some random non-register token, just ignore it. if (Info.RegisterPrefix.empty()) return 0; - + // Otherwise, we have something invalid prefixed with the register prefix, // such as %foo. std::string Err = "unable to find register for '" + RegName.str() + @@ -775,7 +771,6 @@ getSingletonRegisterForAsmOperand(unsigned i, const AsmMatcherInfo &Info) const{ throw TGError(TheDef->getLoc(), Err); } - static std::string getEnumNameForToken(StringRef Str) { std::string Res; @@ -876,7 +871,7 @@ BuildRegisterClasses(SmallPtrSet &SingletonRegisters) { ContainingSet = *it; continue; } - + std::set Tmp; std::swap(Tmp, ContainingSet); std::insert_iterator< std::set > II(ContainingSet, @@ -1013,14 +1008,13 @@ void AsmMatcherInfo::BuildOperandClasses() { } } -AsmMatcherInfo::AsmMatcherInfo(Record *asmParser, - CodeGenTarget &target, +AsmMatcherInfo::AsmMatcherInfo(Record *asmParser, + CodeGenTarget &target, RecordKeeper &records) : Records(records), AsmParser(asmParser), Target(target), RegisterPrefix(AsmParser->getValueAsString("RegisterPrefix")) { } - void AsmMatcherInfo::BuildInfo() { // Build information about all of the AssemblerPredicates. std::vector AllPredicates = @@ -1030,17 +1024,17 @@ void AsmMatcherInfo::BuildInfo() { // Ignore predicates that are not intended for the assembler. if (!Pred->getValueAsBit("AssemblerMatcherPredicate")) continue; - + if (Pred->getName().empty()) throw TGError(Pred->getLoc(), "Predicate has no name!"); - + unsigned FeatureNo = SubtargetFeatures.size(); SubtargetFeatures[Pred] = new SubtargetFeatureInfo(Pred, FeatureNo); assert(FeatureNo < 32 && "Too many subtarget features!"); } StringRef CommentDelimiter = AsmParser->getValueAsString("CommentDelimiter"); - + // Parse the instructions; we need to do this first so that we can gather the // singleton register classes. SmallPtrSet SingletonRegisters; @@ -1056,15 +1050,15 @@ void AsmMatcherInfo::BuildInfo() { // Ignore "codegen only" instructions. if (CGI.TheDef->getValueAsBit("isCodeGenOnly")) continue; - + // Validate the operand list to ensure we can handle this instruction. for (unsigned i = 0, e = CGI.Operands.size(); i != e; ++i) { const CGIOperandList::OperandInfo &OI = CGI.Operands[i]; - + // Validate tied operands. if (OI.getTiedRegister() != -1) { - // If we have a tied operand that consists of multiple MCOperands, reject - // it. We reject aliases and ignore instructions for now. + // If we have a tied operand that consists of multiple MCOperands, + // reject it. We reject aliases and ignore instructions for now. if (OI.MINumOperands != 1) { // FIXME: Should reject these. The ARM backend hits this with $lane // in a bunch of instructions. It is unclear what the right answer is. @@ -1077,26 +1071,26 @@ void AsmMatcherInfo::BuildInfo() { } } } - + OwningPtr II(new MatchableInfo(CGI)); II->Initialize(*this, SingletonRegisters); - + // Ignore instructions which shouldn't be matched and diagnose invalid // instruction definitions with an error. if (!II->Validate(CommentDelimiter, true)) continue; - + // Ignore "Int_*" and "*_Int" instructions, which are internal aliases. // // FIXME: This is a total hack. if (StringRef(II->TheDef->getName()).startswith("Int_") || StringRef(II->TheDef->getName()).endswith("_Int")) continue; - + Matchables.push_back(II.take()); } - + // Parse all of the InstAlias definitions and stick them in the list of // matchables. std::vector AllInstAliases = @@ -1112,12 +1106,12 @@ void AsmMatcherInfo::BuildInfo() { continue; OwningPtr II(new MatchableInfo(Alias)); - + II->Initialize(*this, SingletonRegisters); - + // Validate the alias definitions. II->Validate(CommentDelimiter, false); - + Matchables.push_back(II.take()); } @@ -1158,20 +1152,20 @@ void AsmMatcherInfo::BuildInfo() { Op.Class = getTokenClass(Token); continue; } - + // Otherwise this is an operand reference. StringRef OperandName; if (Token[1] == '{') OperandName = Token.substr(2, Token.size() - 3); else OperandName = Token.substr(1); - + if (II->DefRec.is()) BuildInstructionOperandReference(II, OperandName, i); else BuildAliasOperandReference(II, OperandName, Op); } - + if (II->DefRec.is()) II->BuildInstructionResultOperands(); else @@ -1191,7 +1185,7 @@ BuildInstructionOperandReference(MatchableInfo *II, const CodeGenInstruction &CGI = *II->DefRec.get(); const CGIOperandList &Operands = CGI.Operands; MatchableInfo::AsmOperand *Op = &II->AsmOperands[AsmOpIdx]; - + // Map this token to an operand. unsigned Idx; if (!Operands.hasOperandNamed(OperandName, Idx)) @@ -1238,7 +1232,7 @@ BuildInstructionOperandReference(MatchableInfo *II, OperandName = Operands[Idx.first].Name; Op->SubOpIdx = Idx.second; } - + Op->SrcOpName = OperandName; } @@ -1249,7 +1243,7 @@ void AsmMatcherInfo::BuildAliasOperandReference(MatchableInfo *II, StringRef OperandName, MatchableInfo::AsmOperand &Op) { const CodeGenInstAlias &CGA = *II->DefRec.get(); - + // Set up the operand class. for (unsigned i = 0, e = CGA.ResultOperands.size(); i != e; ++i) if (CGA.ResultOperands[i].isRecord() && @@ -1270,7 +1264,7 @@ void AsmMatcherInfo::BuildAliasOperandReference(MatchableInfo *II, void MatchableInfo::BuildInstructionResultOperands() { const CodeGenInstruction *ResultInst = getResultInst(); - + // Loop over all operands of the result instruction, determining how to // populate them. for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) { @@ -1282,7 +1276,7 @@ void MatchableInfo::BuildInstructionResultOperands() { ResOperands.push_back(ResOperand::getTiedOp(TiedOp)); continue; } - + // Find out what operand from the asmparser this MCInst operand comes from. int SrcOperand = FindAsmOperandNamed(OpInfo.Name); if (OpInfo.Name.empty() || SrcOperand == -1) @@ -1310,14 +1304,14 @@ void MatchableInfo::BuildInstructionResultOperands() { void MatchableInfo::BuildAliasResultOperands() { const CodeGenInstAlias &CGA = *DefRec.get(); const CodeGenInstruction *ResultInst = getResultInst(); - + // Loop over all operands of the result instruction, determining how to // populate them. unsigned AliasOpNo = 0; unsigned LastOpNo = CGA.ResultInstOperandIndex.size(); for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) { const CGIOperandList::OperandInfo *OpInfo = &ResultInst->Operands[i]; - + // If this is a tied operand, just copy from the previously handled operand. int TiedOp = OpInfo->getTiedRegister(); if (TiedOp != -1) { @@ -1398,7 +1392,7 @@ static void EmitConvertToMCInst(CodeGenTarget &Target, std::string Signature = "Convert"; std::string CaseBody; raw_string_ostream CaseOS(CaseBody); - + // Compute the convert enum and the case body. for (unsigned i = 0, e = II.ResOperands.size(); i != e; ++i) { const MatchableInfo::ResOperand &OpInfo = II.ResOperands[i]; @@ -1408,7 +1402,7 @@ static void EmitConvertToMCInst(CodeGenTarget &Target, case MatchableInfo::ResOperand::RenderAsmOperand: { // This comes from something we parsed. MatchableInfo::AsmOperand &Op = II.AsmOperands[OpInfo.AsmOperandNum]; - + // Registers are always converted the same, don't duplicate the // conversion function based on them. Signature += "__"; @@ -1418,13 +1412,13 @@ static void EmitConvertToMCInst(CodeGenTarget &Target, Signature += Op.Class->ClassName; Signature += utostr(OpInfo.MINumOperands); Signature += "_" + itostr(OpInfo.AsmOperandNum); - + CaseOS << " ((" << TargetOperandClass << "*)Operands[" << (OpInfo.AsmOperandNum+1) << "])->" << Op.Class->RenderMethod << "(Inst, " << OpInfo.MINumOperands << ");\n"; break; } - + case MatchableInfo::ResOperand::TiedOperand: { // If this operand is tied to a previous one, just copy the MCInst // operand from the earlier one.We can only tie single MCOperand values. @@ -1450,10 +1444,10 @@ static void EmitConvertToMCInst(CodeGenTarget &Target, CaseOS << " Inst.addOperand(MCOperand::CreateReg(" << N << "));\n"; Signature += "__reg" + OpInfo.Register->getName(); } - } + } } } - + II.ConversionFnKind = Signature; // Check if we have already generated this signature. @@ -1538,9 +1532,9 @@ static void EmitClassifyOperand(AsmMatcherInfo &Info, OS << " }\n\n"; // Classify user defined operands. To do so, we need to perform a topological - // sort of the superclass relationship graph so that we always match the + // sort of the superclass relationship graph so that we always match the // narrowest type first. - + // Collect the incoming edge counts for each class. std::map IncomingEdges; for (std::vector::iterator it = Info.Classes.begin(), @@ -1549,12 +1543,12 @@ static void EmitClassifyOperand(AsmMatcherInfo &Info, if (!CI.isUserClass()) continue; - + for (std::vector::iterator SI = CI.SuperClasses.begin(), SE = CI.SuperClasses.end(); SI != SE; ++SI) ++IncomingEdges[*SI]; } - + // Initialize a worklist of classes with no incoming edges. std::vector LeafClasses; for (std::vector::iterator it = Info.Classes.begin(), @@ -1562,17 +1556,17 @@ static void EmitClassifyOperand(AsmMatcherInfo &Info, if (!IncomingEdges[*it]) LeafClasses.push_back(*it); } - + // Iteratively pop the list, process that class, and update the incoming // edge counts for its super classes. When a superclass reaches zero // incoming edges, push it onto the worklist for processing. while (!LeafClasses.empty()) { ClassInfo &CI = *LeafClasses.back(); LeafClasses.pop_back(); - + if (!CI.isUserClass()) continue; - + OS << " // '" << CI.ClassName << "' class"; if (!CI.SuperClasses.empty()) { OS << ", subclass of "; @@ -1580,7 +1574,7 @@ static void EmitClassifyOperand(AsmMatcherInfo &Info, if (i) OS << ", "; OS << "'" << CI.SuperClasses[i]->ClassName << "'"; assert(CI < *CI.SuperClasses[i] && "Invalid class relation!"); - + --IncomingEdges[CI.SuperClasses[i]]; if (!IncomingEdges[CI.SuperClasses[i]]) LeafClasses.push_back(CI.SuperClasses[i]); @@ -1596,11 +1590,11 @@ static void EmitClassifyOperand(AsmMatcherInfo &Info, OS << " assert(Operand." << CI.SuperClasses[i]->PredicateMethod << "() && \"Invalid class relationship!\");\n"; } - + OS << " return " << CI.Name << ";\n"; OS << " }\n\n"; } - + OS << " return InvalidMatchClass;\n"; OS << "}\n\n"; } @@ -1652,8 +1646,6 @@ static void EmitIsSubclass(CodeGenTarget &Target, OS << "}\n\n"; } - - /// EmitMatchTokenString - Emit the function to match a token string to the /// appropriate match class value. static void EmitMatchTokenString(CodeGenTarget &Target, @@ -1749,18 +1741,18 @@ static std::string GetAliasRequiredFeatures(Record *R, unsigned NumFeatures = 0; for (unsigned i = 0, e = ReqFeatures.size(); i != e; ++i) { SubtargetFeatureInfo *F = Info.getSubtargetFeature(ReqFeatures[i]); - + if (F == 0) throw TGError(R->getLoc(), "Predicate '" + ReqFeatures[i]->getName() + "' is not marked as an AssemblerPredicate!"); - + if (NumFeatures) Result += '|'; - + Result += F->getEnumName(); ++NumFeatures; } - + if (NumFeatures > 1) Result = '(' + Result + ')'; return Result; @@ -1779,11 +1771,11 @@ static bool EmitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info) { OS << "static void ApplyMnemonicAliases(StringRef &Mnemonic, " "unsigned Features) {\n"; - + // Keep track of all the aliases from a mnemonic. Use an std::map so that the // iteration order of the map is stable. std::map > AliasesFromMnemonic; - + for (unsigned i = 0, e = Aliases.size(); i != e; ++i) { Record *R = Aliases[i]; AliasesFromMnemonic[R->getValueAsString("FromMnemonic")].push_back(R); @@ -1802,11 +1794,11 @@ static bool EmitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info) { // emit it last. std::string MatchCode; int AliasWithNoPredicate = -1; - + for (unsigned i = 0, e = ToVec.size(); i != e; ++i) { Record *R = ToVec[i]; std::string FeatureMask = GetAliasRequiredFeatures(R, Info); - + // If this unconditionally matches, remember it for later and diagnose // duplicates. if (FeatureMask.empty()) { @@ -1816,33 +1808,32 @@ static bool EmitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info) { "two MnemonicAliases with the same 'from' mnemonic!"); throw TGError(R->getLoc(), "this is the other MnemonicAlias."); } - + AliasWithNoPredicate = i; continue; } - + if (!MatchCode.empty()) MatchCode += "else "; MatchCode += "if ((Features & " + FeatureMask + ") == "+FeatureMask+")\n"; MatchCode += " Mnemonic = \"" +R->getValueAsString("ToMnemonic")+"\";\n"; } - + if (AliasWithNoPredicate != -1) { Record *R = ToVec[AliasWithNoPredicate]; if (!MatchCode.empty()) MatchCode += "else\n "; MatchCode += "Mnemonic = \"" + R->getValueAsString("ToMnemonic")+"\";\n"; } - + MatchCode += "return;"; Cases.push_back(std::make_pair(I->first, MatchCode)); } - - + StringMatcher("Mnemonic", Cases, OS).Emit(); OS << "}\n\n"; - + return true; } @@ -1928,7 +1919,7 @@ void AsmMatcherEmitter::run(raw_ostream &OS) { // Generate the function that remaps for mnemonic aliases. bool HasMnemonicAliases = EmitMnemonicAliases(OS, Info); - + // Generate the unified function to convert operands into an MCInst. EmitConvertToMCInst(Target, Info.Matchables, OS); @@ -1954,7 +1945,6 @@ void AsmMatcherEmitter::run(raw_ostream &OS) { it != ie; ++it) MaxNumOperands = std::max(MaxNumOperands, (*it)->AsmOperands.size()); - // Emit the static match table; unused classes get initalized to 0 which is // guaranteed to be InvalidMatchClass. // @@ -2042,7 +2032,7 @@ void AsmMatcherEmitter::run(raw_ostream &OS) { OS << " // Process all MnemonicAliases to remap the mnemonic.\n"; OS << " ApplyMnemonicAliases(Mnemonic, AvailableFeatures);\n\n"; } - + // Emit code to compute the class list for this operand vector. OS << " // Eliminate obvious mismatches.\n"; OS << " if (Operands.size() > " << (MaxNumOperands+1) << ") {\n"; -- cgit v1.2.3