From d35da5055ba01057ee08b9feb987e02335c6f44f Mon Sep 17 00:00:00 2001 From: Bill Schmidt Date: Wed, 22 May 2013 20:45:11 +0000 Subject: Recognize ValueType operands in source patterns for fast-isel. Currently the fast-isel table generator recognizes registers, register classes, and immediates for source pattern operands. ValueType operands are not recognized. This is not a problem for existing targets with fast-isel support, but will not work for targets like PowerPC and SPARC that use types in source patterns. The proposed patch allows ValueType operands and treats them in the same manner as register classes. There is no convenient way to map from a ValueType to a register class, but there's no need to do so. The table generator already requires that all types in the source pattern be identical, and we know the register class of the output operand already. So we just assign that register class to any ValueType operands we encounter. No functional effect on existing targets. Testing deferred until the PowerPC target implements fast-isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182512 91177308-0d34-0410-b5e6-96231b3b80d8 --- utils/TableGen/FastISelEmitter.cpp | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'utils') diff --git a/utils/TableGen/FastISelEmitter.cpp b/utils/TableGen/FastISelEmitter.cpp index 8b1e7f9256..ce7f8c8163 100644 --- a/utils/TableGen/FastISelEmitter.cpp +++ b/utils/TableGen/FastISelEmitter.cpp @@ -173,7 +173,8 @@ struct OperandsSignature { /// bool initialize(TreePatternNode *InstPatNode, const CodeGenTarget &Target, MVT::SimpleValueType VT, - ImmPredicateSet &ImmediatePredicates) { + ImmPredicateSet &ImmediatePredicates, + const CodeGenRegisterClass *OrigDstRC) { if (InstPatNode->isLeaf()) return false; @@ -258,7 +259,9 @@ struct OperandsSignature { RC = &Target.getRegisterClass(OpLeafRec); else if (OpLeafRec->isSubClassOf("Register")) RC = Target.getRegBank().getRegClassForRegister(OpLeafRec); - else + else if (OpLeafRec->isSubClassOf("ValueType")) { + RC = OrigDstRC; + } else return false; // For now, this needs to be a register class of some sort. @@ -503,7 +506,8 @@ void FastISelMap::collectPatterns(CodeGenDAGPatterns &CGP) { // Check all the operands. OperandsSignature Operands; - if (!Operands.initialize(InstPatNode, Target, VT, ImmediatePredicates)) + if (!Operands.initialize(InstPatNode, Target, VT, ImmediatePredicates, + DstRC)) continue; std::vector* PhysRegInputs = new std::vector(); -- cgit v1.2.3