1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
|
; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 -disable-mips-delay-filler %s -o - \
; RUN: | llvm-objdump -disassemble -triple mips64el - | FileCheck %s
; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 %s -o - \
; RUN: | llvm-objdump -disassemble -triple mips64el - | FileCheck %s
define i64 @f3(i64 %a0) nounwind readnone {
entry:
; CHECK: dsll ${{[0-9]+}}, ${{[0-9]+}}, 10
%shl = shl i64 %a0, 10
ret i64 %shl
}
define i64 @f4(i64 %a0) nounwind readnone {
entry:
; CHECK: dsra ${{[0-9]+}}, ${{[0-9]+}}, 10
%shr = ashr i64 %a0, 10
ret i64 %shr
}
define i64 @f5(i64 %a0) nounwind readnone {
entry:
; CHECK: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 10
%shr = lshr i64 %a0, 10
ret i64 %shr
}
define i64 @f6(i64 %a0) nounwind readnone {
entry:
; CHECK: dsll32 ${{[0-9]+}}, ${{[0-9]+}}, 8
%shl = shl i64 %a0, 40
ret i64 %shl
}
define i64 @f7(i64 %a0) nounwind readnone {
entry:
; CHECK: dsra32 ${{[0-9]+}}, ${{[0-9]+}}, 8
%shr = ashr i64 %a0, 40
ret i64 %shr
}
define i64 @f8(i64 %a0) nounwind readnone {
entry:
; CHECK: dsrl32 ${{[0-9]+}}, ${{[0-9]+}}, 8
%shr = lshr i64 %a0, 40
ret i64 %shr
}
|
