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authorNadav Rotem <nadav.rotem@intel.com>2012-02-13 12:42:26 +0000
committerNadav Rotem <nadav.rotem@intel.com>2012-02-13 12:42:26 +0000
commit0877fdf30bb626217f635547ca90741a8c7558ad (patch)
treeb40be49d410fe8754a65458b296215e233c917ae
parent4a5d7e300eef8d14fefac5ee78b5cc9ffca49293 (diff)
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Fix a bug in DAGCombine for the optimization of BUILD_VECTOR. We cant generate a shuffle node from two vectors of different types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150383 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/CodeGen/SelectionDAG/DAGCombiner.cpp8
-rw-r--r--test/CodeGen/X86/2012-02-12-dagco.ll16
2 files changed, 22 insertions, 2 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 9fa5572e81..f51e7215d5 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -7385,9 +7385,13 @@ SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
// If VecIn2 is unused then change it to undef.
VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
+ // Check that we were able to transform all incoming values to the same type.
+ if (VecIn2.getValueType() != VecIn1.getValueType() ||
+ VecIn1.getValueType() != VT)
+ return SDValue();
+
// Only type-legal BUILD_VECTOR nodes are converted to shuffle nodes.
- if (!isTypeLegal(VT) || !isTypeLegal(VecIn1.getValueType()) ||
- !isTypeLegal(VecIn2.getValueType()))
+ if (!isTypeLegal(VT))
return SDValue();
// Return the new VECTOR_SHUFFLE node.
diff --git a/test/CodeGen/X86/2012-02-12-dagco.ll b/test/CodeGen/X86/2012-02-12-dagco.ll
new file mode 100644
index 0000000000..13723a2299
--- /dev/null
+++ b/test/CodeGen/X86/2012-02-12-dagco.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx
+target triple = "x86_64-unknown-linux-gnu"
+; Make sure we are not crashing on this one
+define void @dagco_crash() {
+entry:
+ %srcval.i411.i = load <4 x i64>* undef, align 1
+ %0 = extractelement <4 x i64> %srcval.i411.i, i32 3
+ %srcval.i409.i = load <2 x i64>* undef, align 1
+ %1 = extractelement <2 x i64> %srcval.i409.i, i32 0
+ %2 = insertelement <8 x i64> undef, i64 %0, i32 5
+ %3 = insertelement <8 x i64> %2, i64 %1, i32 6
+ %4 = insertelement <8 x i64> %3, i64 undef, i32 7
+ store <8 x i64> %4, <8 x i64> addrspace(1)* undef, align 64
+ unreachable
+}
+