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| author | Dan Gohman <gohman@apple.com> | 2007-11-19 15:15:03 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2007-11-19 15:15:03 +0000 |
| commit | 089617d9e3acc242151a007e7a051ed2fb200b1f (patch) | |
| tree | b304a0eec3cde7be5e7e6bf61322224f093d8169 | |
| parent | f1c922181b0e9ce58b95257df9991f00d4f4202b (diff) | |
| download | llvm-089617d9e3acc242151a007e7a051ed2fb200b1f.tar.gz llvm-089617d9e3acc242151a007e7a051ed2fb200b1f.tar.bz2 llvm-089617d9e3acc242151a007e7a051ed2fb200b1f.tar.xz | |
Add support in SplitVectorOp for remainder operators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44233 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 5 | ||||
| -rw-r--r-- | test/CodeGen/X86/split-vector-rem.ll | 15 |
2 files changed, 19 insertions, 1 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 4ddcbf6bab..c6b4662b2b 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -6341,7 +6341,10 @@ void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo, case ISD::FPOW: case ISD::AND: case ISD::OR: - case ISD::XOR: { + case ISD::XOR: + case ISD::UREM: + case ISD::SREM: + case ISD::FREM: { SDOperand LL, LH, RL, RH; SplitVectorOp(Node->getOperand(0), LL, LH); SplitVectorOp(Node->getOperand(1), RL, RH); diff --git a/test/CodeGen/X86/split-vector-rem.ll b/test/CodeGen/X86/split-vector-rem.ll new file mode 100644 index 0000000000..8c88769be7 --- /dev/null +++ b/test/CodeGen/X86/split-vector-rem.ll @@ -0,0 +1,15 @@ +; RUN: llvm-as < %s | llc -march=x86-64 | grep div | count 16 +; RUN: llvm-as < %s | llc -march=x86-64 | grep fmodf | count 8 + +define <8 x i32> @foo(<8 x i32> %t, <8 x i32> %u) { + %m = srem <8 x i32> %t, %u + ret <8 x i32> %m +} +define <8 x i32> @bar(<8 x i32> %t, <8 x i32> %u) { + %m = urem <8 x i32> %t, %u + ret <8 x i32> %m +} +define <8 x float> @qux(<8 x float> %t, <8 x float> %u) { + %m = frem <8 x float> %t, %u + ret <8 x float> %m +} |