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author | Jim Laskey <jlaskey@mac.com> | 2005-10-19 13:34:52 +0000 |
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committer | Jim Laskey <jlaskey@mac.com> | 2005-10-19 13:34:52 +0000 |
commit | 0de8796e68d49d57f4135aa40a1c72b03aa8ecca (patch) | |
tree | 1fcf99c527ee9876be7cc735bc50da5828f697f3 | |
parent | 2f041d49a9750b714a8ceebe28038c78c6c40a4e (diff) | |
download | llvm-0de8796e68d49d57f4135aa40a1c72b03aa8ecca.tar.gz llvm-0de8796e68d49d57f4135aa40a1c72b03aa8ecca.tar.bz2 llvm-0de8796e68d49d57f4135aa40a1c72b03aa8ecca.tar.xz |
Push processor descriptions to the top of target and add command line info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23820 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/PowerPC/PPCSchedule.td | 46 | ||||
-rw-r--r-- | lib/Target/PowerPC/PPCScheduleG3.td | 2 | ||||
-rw-r--r-- | lib/Target/PowerPC/PPCScheduleG4.td | 2 | ||||
-rw-r--r-- | lib/Target/PowerPC/PPCScheduleG4Plus.td | 2 | ||||
-rw-r--r-- | lib/Target/PowerPC/PPCScheduleG5.td | 2 | ||||
-rw-r--r-- | lib/Target/Target.td | 39 | ||||
-rw-r--r-- | lib/Target/TargetSchedule.td | 10 |
7 files changed, 80 insertions, 23 deletions
diff --git a/lib/Target/PowerPC/PPCSchedule.td b/lib/Target/PowerPC/PPCSchedule.td index dc12e76f7f..f02e52d39c 100644 --- a/lib/Target/PowerPC/PPCSchedule.td +++ b/lib/Target/PowerPC/PPCSchedule.td @@ -7,20 +7,11 @@ // //===----------------------------------------------------------------------===// -#include "../TargetSchedule.td" - -//===----------------------------------------------------------------------===// -// PowerPC chips sets supported by scheduling (Apple naming) -// -def G3 : Processor; -def G4 : Processor; -def G4Plus : Processor; -def G5 : Processor; +#include "../Target.td" //===----------------------------------------------------------------------===// // Functional units across PowerPC chips sets // -def NoUnit : FuncUnit; // Instruction not supported on chip set def BPU : FuncUnit; // Branch unit def SLU : FuncUnit; // Store/load unit def SRU : FuncUnit; // special register unit @@ -518,3 +509,38 @@ def VecVSR : InstrItinClass; // xoris IntGeneral // + +//===----------------------------------------------------------------------===// +// PowerPC Subtarget features. +// + +def F64Bit : SubtargetFeature<"64bit", + "Should 64 bit instructions be used">; +def F64BitRegs : SubtargetFeature<"64bitregs", + "Should 64 bit registers be used">; +def FAltivec : SubtargetFeature<"altivec", + "Should Altivec instructions be used">; +def FGPUL : SubtargetFeature<"gpul", + "Should GPUL instructions be used">; +def FFSQRT : SubtargetFeature<"fsqrt", + "Should the fsqrt instruction be used">; + +//===----------------------------------------------------------------------===// +// PowerPC chips sets supported +// + +def : Processor<"601", G3Itineraries, []>; +def : Processor<"602", G3Itineraries, []>; +def : Processor<"603", G3Itineraries, []>; +def : Processor<"604", G3Itineraries, []>; +def : Processor<"750", G3Itineraries, []>; +def : Processor<"7400", G4Itineraries, [FAltivec]>; +def : Processor<"g4", G4Itineraries, [FAltivec]>; +def : Processor<"7450", G4PlusItineraries, [FAltivec]>; +def : Processor<"g4+", G4PlusItineraries, [FAltivec]>; +def : Processor<"970", G5Itineraries, + [FAltivec, FGPUL, FFSQRT, F64Bit, F64BitRegs]>; +def : Processor<"g5", G5Itineraries, + [FAltivec, FGPUL, FFSQRT, F64Bit, F64BitRegs]>; + + diff --git a/lib/Target/PowerPC/PPCScheduleG3.td b/lib/Target/PowerPC/PPCScheduleG3.td index 3931e2084b..30cc8652c7 100644 --- a/lib/Target/PowerPC/PPCScheduleG3.td +++ b/lib/Target/PowerPC/PPCScheduleG3.td @@ -12,7 +12,7 @@ //===----------------------------------------------------------------------===// -def G3Itineraries : ProcessorItineraries<G3, [ +def G3Itineraries : ProcessorItineraries<[ InstrItinData<IntGeneral , [InstrStage<1, [IU1, IU2]>]>, InstrItinData<IntCompare , [InstrStage<1, [IU1, IU2]>]>, InstrItinData<IntDivW , [InstrStage<19, [IU1]>]>, diff --git a/lib/Target/PowerPC/PPCScheduleG4.td b/lib/Target/PowerPC/PPCScheduleG4.td index 6984ae9b0a..2b1818a24f 100644 --- a/lib/Target/PowerPC/PPCScheduleG4.td +++ b/lib/Target/PowerPC/PPCScheduleG4.td @@ -11,7 +11,7 @@ // //===----------------------------------------------------------------------===// -def G4Itineraries : ProcessorItineraries<G4, [ +def G4Itineraries : ProcessorItineraries<[ InstrItinData<IntGeneral , [InstrStage<1, [IU1, IU2]>]>, InstrItinData<IntCompare , [InstrStage<1, [IU1, IU2]>]>, InstrItinData<IntDivW , [InstrStage<19, [IU1]>]>, diff --git a/lib/Target/PowerPC/PPCScheduleG4Plus.td b/lib/Target/PowerPC/PPCScheduleG4Plus.td index 7d028c2c65..d5b95289c6 100644 --- a/lib/Target/PowerPC/PPCScheduleG4Plus.td +++ b/lib/Target/PowerPC/PPCScheduleG4Plus.td @@ -11,7 +11,7 @@ // //===----------------------------------------------------------------------===// -def G4PlusItineraries : ProcessorItineraries<G4Plus, [ +def G4PlusItineraries : ProcessorItineraries<[ InstrItinData<IntGeneral , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>, InstrItinData<IntCompare , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>, InstrItinData<IntDivW , [InstrStage<23, [IU2]>]>, diff --git a/lib/Target/PowerPC/PPCScheduleG5.td b/lib/Target/PowerPC/PPCScheduleG5.td index 4738b89299..a34ff9909d 100644 --- a/lib/Target/PowerPC/PPCScheduleG5.td +++ b/lib/Target/PowerPC/PPCScheduleG5.td @@ -11,7 +11,7 @@ // //===----------------------------------------------------------------------===// -def G5Itineraries : ProcessorItineraries<G5, [ +def G5Itineraries : ProcessorItineraries<[ InstrItinData<IntGeneral , [InstrStage<2, [IU1, IU2]>]>, InstrItinData<IntCompare , [InstrStage<3, [IU1, IU2]>]>, InstrItinData<IntDivD , [InstrStage<68, [IU1]>]>, diff --git a/lib/Target/Target.td b/lib/Target/Target.td index 4e36223123..994a71df21 100644 --- a/lib/Target/Target.td +++ b/lib/Target/Target.td @@ -242,6 +242,45 @@ class Target { } //===----------------------------------------------------------------------===// +// Pull in the common support for scheduling +// +include "../TargetSchedule.td" + +//===----------------------------------------------------------------------===// +// SubtargetFeature - A characteristic of the chip set. +// +class SubtargetFeature<string n, string d> { + // Name - Feature name. Used by command line (-mattr=) to determine the + // appropriate target chip. + // + string Name = n; + + // Desc - Feature description. Used by command line (-mattr=) to display help + // information. + // + string Desc = d; +} + +//===----------------------------------------------------------------------===// +// Processor chip sets - These values represent each of the chip sets supported +// by the scheduler. Each Processor definition requires corresponding +// instruction itineraries. +// +class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> { + // Name - Chip set name. Used by command line (-mcpu=) to determine the + // appropriate target chip. + // + string Name = n; + + // ProcItin - The scheduling information for the target processor. + // + ProcessorItineraries ProcItin = pi; + + // Features - list of + list<SubtargetFeature> Features; +} + +//===----------------------------------------------------------------------===// // Pull in the common support for DAG isel generation // include "../TargetSelectionDAG.td" diff --git a/lib/Target/TargetSchedule.td b/lib/Target/TargetSchedule.td index 9b4ad022d8..89c00cdc70 100644 --- a/lib/Target/TargetSchedule.td +++ b/lib/Target/TargetSchedule.td @@ -13,13 +13,6 @@ //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// -// Processor chip sets - These values represent each of the chip sets supported -// by the scheduler. Each Processor definition requires corresponding -// instruction itineraries. -// -class Processor; - -//===----------------------------------------------------------------------===// // Processor functional unit - These values represent the function units // available across all chip sets for the target. Eg., IntUnit, FPUnit, ... // These may be independent values for each chip set or may be shared across @@ -68,7 +61,6 @@ class InstrItinData<InstrItinClass Class, list<InstrStage> stages> { // Processor itineraries - These values represent the set of all itinerary // classes for a given chip set. // -class ProcessorItineraries<Processor proc, list<InstrItinData> iid> { - Processor Proc = proc; +class ProcessorItineraries<list<InstrItinData> iid> { list<InstrItinData> IID = iid; } |