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| author | Jack Carter <jcarter@mips.com> | 2012-07-02 23:35:23 +0000 |
|---|---|---|
| committer | Jack Carter <jcarter@mips.com> | 2012-07-02 23:35:23 +0000 |
| commit | 10de025a67aa37112d5d4cd703925a7c1996422a (patch) | |
| tree | 01b6b0506dc61ab43904a7b71b5a499ba8376c1e | |
| parent | 80c1b38eff2fb3200cdddb1ef6641d64de8496a8 (diff) | |
| download | llvm-10de025a67aa37112d5d4cd703925a7c1996422a.tar.gz llvm-10de025a67aa37112d5d4cd703925a7c1996422a.tar.bz2 llvm-10de025a67aa37112d5d4cd703925a7c1996422a.tar.xz | |
mips32 long long register inline asm constraint support.
inlineasm-cnstrnt-bad-r-1.ll is NOT supposed to fail, so it was removed. This resulted in the removal of a negative test (inlineasm-cnstrnt-bad-r-1.ll)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159625 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/Mips/MipsISelLowering.cpp | 2 | ||||
| -rw-r--r-- | test/CodeGen/Mips/inlineasm-operand-code.ll | 6 |
2 files changed, 8 insertions, 0 deletions
diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp index abf22bd804..a7e2aa32fc 100644 --- a/lib/Target/Mips/MipsISelLowering.cpp +++ b/lib/Target/Mips/MipsISelLowering.cpp @@ -3355,6 +3355,8 @@ getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const case 'r': if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) return std::make_pair(0U, &Mips::CPURegsRegClass); + if (VT == MVT::i64 && !HasMips64) + return std::make_pair(0U, &Mips::CPURegsRegClass); if (VT == MVT::i64 && HasMips64) return std::make_pair(0U, &Mips::CPU64RegsRegClass); // This will generate an error message diff --git a/test/CodeGen/Mips/inlineasm-operand-code.ll b/test/CodeGen/Mips/inlineasm-operand-code.ll index ca4f3e4c5a..d75f7f2f80 100644 --- a/test/CodeGen/Mips/inlineasm-operand-code.ll +++ b/test/CodeGen/Mips/inlineasm-operand-code.ll @@ -41,5 +41,11 @@ entry: ;CHECK: #NO_APP tail call i32 asm sideeffect "addi $0,$1,${2:z}", "=r,r,I"(i32 7, i32 0) nounwind +; a long long in 32 bit mode (use to assert) +;CHECK: #APP +;CHECK: addi ${{[0-9]+}},${{[0-9]+}},3 +;CHECK: #NO_APP + tail call i64 asm sideeffect "addi $0,$1,$2 \0A\09", "=r,r,X"(i64 1229801703532086340, i64 3) nounwind + ret i32 0 } |