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| author | Reed Kotler <rkotler@mips.com> | 2013-02-18 04:55:38 +0000 |
|---|---|---|
| committer | Reed Kotler <rkotler@mips.com> | 2013-02-18 04:55:38 +0000 |
| commit | 139748f1c180d4f2d55f31b321e9cfe87b06eb64 (patch) | |
| tree | 2d18c5b031b39d32c4e96faf81595f7786e38267 | |
| parent | dabfebb5c61e49ab23c5828953506d965bcf7401 (diff) | |
| download | llvm-139748f1c180d4f2d55f31b321e9cfe87b06eb64.tar.gz llvm-139748f1c180d4f2d55f31b321e9cfe87b06eb64.tar.bz2 llvm-139748f1c180d4f2d55f31b321e9cfe87b06eb64.tar.xz | |
Expand pseudo/macro BteqzT8SltuX16 . There is no test case because
at this time, llvm is generating a different but equivalent pattern
that would lead to this instruction. I am trying to think of a way
to get it to generate this. If I can't, I may just remove the pseudo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175419 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/Mips/Mips16InstrInfo.cpp | 5 | ||||
| -rw-r--r-- | lib/Target/Mips/Mips16InstrInfo.td | 2 |
2 files changed, 7 insertions, 0 deletions
diff --git a/lib/Target/Mips/Mips16InstrInfo.cpp b/lib/Target/Mips/Mips16InstrInfo.cpp index ba1002ed4c..e0277ff5a0 100644 --- a/lib/Target/Mips/Mips16InstrInfo.cpp +++ b/lib/Target/Mips/Mips16InstrInfo.cpp @@ -142,6 +142,11 @@ bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const { case Mips::BteqzT8SltX16: ExpandFEXT_T8I816_ins(MBB, MI, Mips::BteqzX16, Mips::SltRxRy16); break; + case Mips::BteqzT8SltuX16: + // TBD: figure out a way to get this or remove the instruction + // altogether. + ExpandFEXT_T8I816_ins(MBB, MI, Mips::BteqzX16, Mips::SltuRxRy16); + break; case Mips::BtnezT8CmpX16: ExpandFEXT_T8I816_ins(MBB, MI, Mips::BtnezX16, Mips::CmpRxRy16); break; diff --git a/lib/Target/Mips/Mips16InstrInfo.td b/lib/Target/Mips/Mips16InstrInfo.td index 2ab7b47724..c7adce3a5b 100644 --- a/lib/Target/Mips/Mips16InstrInfo.td +++ b/lib/Target/Mips/Mips16InstrInfo.td @@ -1012,6 +1012,8 @@ def SltCCRxRy16: FCCRR16_ins<"slt">; // Purpose: Set on Less Than Unsigned // To record the result of an unsigned less-than comparison. // +def SltuRxRy16: FRR16_ins<0b00011, "sltu", IIAlu>; + def SltuRxRyRz16: FRRTR16_ins<"sltu"> { let isCodeGenOnly=1; } |