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authorNate Begeman <natebegeman@mac.com>2005-10-13 17:15:37 +0000
committerNate Begeman <natebegeman@mac.com>2005-10-13 17:15:37 +0000
commit144ff660e66845a575586bc4092c0cf349b5bfb9 (patch)
treef689777f096c9baff69d05de68552266639a76bd
parent53c523c00e6c160bb8e3a6931497eb87d82eb108 (diff)
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Add support to Legalize for expanding i64 sextload/zextload into hi and lo
parts. This should fix the crafty and signed long long unit test failure on x86 last night. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23711 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/CodeGen/SelectionDAG/LegalizeDAG.cpp35
1 files changed, 35 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 0c08d5a525..8ea3eb7884 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -3101,6 +3101,41 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
Hi = LegalizeOp(Hi);
break;
}
+ case ISD::SEXTLOAD: {
+ SDOperand Chain = LegalizeOp(Node->getOperand(0));
+ SDOperand Ptr = LegalizeOp(Node->getOperand(1));
+ MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
+
+ if (EVT == NVT)
+ Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
+ else
+ Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
+ EVT);
+ // The high part is obtained by SRA'ing all but one of the bits of the lo
+ // part.
+ unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
+ Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1,
+ TLI.getShiftAmountTy()));
+ Lo = LegalizeOp(Lo);
+ Hi = LegalizeOp(Hi);
+ break;
+ }
+ case ISD::ZEXTLOAD: {
+ SDOperand Chain = LegalizeOp(Node->getOperand(0));
+ SDOperand Ptr = LegalizeOp(Node->getOperand(1));
+ MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
+
+ if (EVT == NVT)
+ Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
+ else
+ Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
+ EVT);
+ // The high part is just a zero.
+ Hi = DAG.getConstant(0, NVT);
+ Lo = LegalizeOp(Lo);
+ Hi = LegalizeOp(Hi);
+ break;
+ }
case ISD::ANY_EXTEND: {
SDOperand In;
switch (getTypeAction(Node->getOperand(0).getValueType())) {