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| author | Roman Divacky <rdivacky@freebsd.org> | 2013-10-31 19:22:33 +0000 |
|---|---|---|
| committer | Roman Divacky <rdivacky@freebsd.org> | 2013-10-31 19:22:33 +0000 |
| commit | 1d6d49fbb104781cc3e9da9dcc3e36b6cbcd38b6 (patch) | |
| tree | 0e46baa8967a1a6f6e534964ebae6187c9960268 | |
| parent | 844e7d35d400aa2feb4310d620b9ad8393ed5c17 (diff) | |
| download | llvm-1d6d49fbb104781cc3e9da9dcc3e36b6cbcd38b6.tar.gz llvm-1d6d49fbb104781cc3e9da9dcc3e36b6cbcd38b6.tar.bz2 llvm-1d6d49fbb104781cc3e9da9dcc3e36b6cbcd38b6.tar.xz | |
SparcV9 doesnt have rem instruction either.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193789 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/Sparc/SparcISelLowering.cpp | 8 | ||||
| -rw-r--r-- | test/CodeGen/SPARC/rem.ll | 23 |
2 files changed, 31 insertions, 0 deletions
diff --git a/lib/Target/Sparc/SparcISelLowering.cpp b/lib/Target/Sparc/SparcISelLowering.cpp index c2e16fc219..d0156fa340 100644 --- a/lib/Target/Sparc/SparcISelLowering.cpp +++ b/lib/Target/Sparc/SparcISelLowering.cpp @@ -1341,6 +1341,14 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) setOperationAction(ISD::SREM, MVT::i32, Expand); setOperationAction(ISD::SDIVREM, MVT::i32, Expand); setOperationAction(ISD::UDIVREM, MVT::i32, Expand); + + // ... nor does SparcV9. + if (Subtarget->is64Bit()) { + setOperationAction(ISD::UREM, MVT::i64, Expand); + setOperationAction(ISD::SREM, MVT::i64, Expand); + setOperationAction(ISD::SDIVREM, MVT::i64, Expand); + setOperationAction(ISD::UDIVREM, MVT::i64, Expand); + } // Custom expand fp<->sint setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); diff --git a/test/CodeGen/SPARC/rem.ll b/test/CodeGen/SPARC/rem.ll new file mode 100644 index 0000000000..71f62e4fc1 --- /dev/null +++ b/test/CodeGen/SPARC/rem.ll @@ -0,0 +1,23 @@ +; RUN: llc < %s -march=sparcv9 | FileCheck %s + +; CHECK-LABEL: test1: +; CHECK: sdivx %o0, %o1, %o2 +; CHECK-NEXT: mulx %o2, %o1, %o1 +; CHECK-NEXT: jmp %o7+8 +; CHECK-NEXT: sub %o0, %o1, %o0 + +define i64 @test1(i64 %X, i64 %Y) { + %tmp1 = srem i64 %X, %Y + ret i64 %tmp1 +} + +; CHECK-LABEL: test2: +; CHECK: udivx %o0, %o1, %o2 +; CHECK-NEXT: mulx %o2, %o1, %o1 +; CHECK-NEXT: jmp %o7+8 +; CHECK-NEXT: sub %o0, %o1, %o0 + +define i64 @test2(i64 %X, i64 %Y) { + %tmp1 = urem i64 %X, %Y + ret i64 %tmp1 +} |