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author | Akira Hatanaka <ahatanaka@mips.com> | 2012-12-20 04:20:09 +0000 |
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committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-12-20 04:20:09 +0000 |
commit | 1e7739f6140da773b6e998525d7900fa82670f00 (patch) | |
tree | 9f66500b4bbf2f9d480dc7c32b9442a0dc439eaa | |
parent | 77e85f367c4f69fb95a88419aba1eef2cbab6800 (diff) | |
download | llvm-1e7739f6140da773b6e998525d7900fa82670f00.tar.gz llvm-1e7739f6140da773b6e998525d7900fa82670f00.tar.bz2 llvm-1e7739f6140da773b6e998525d7900fa82670f00.tar.xz |
[mips] Remove asm string parameter from pseudo instructions. Add InstrItinClass
parameter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170661 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/Mips/Mips64InstrInfo.td | 28 | ||||
-rw-r--r-- | lib/Target/Mips/MipsDSPInstrFormats.td | 5 | ||||
-rw-r--r-- | lib/Target/Mips/MipsDSPInstrInfo.td | 2 | ||||
-rw-r--r-- | lib/Target/Mips/MipsInstrFPU.td | 7 | ||||
-rw-r--r-- | lib/Target/Mips/MipsInstrFormats.td | 10 | ||||
-rw-r--r-- | lib/Target/Mips/MipsInstrInfo.td | 81 |
6 files changed, 64 insertions, 69 deletions
diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index 9b4b07b5f7..0a3a500304 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -46,19 +46,19 @@ class Mult64<bits<6> func, string instr_asm, InstrItinClass itin>: class Div64<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>: Div<op, func, instr_asm, itin, CPU64Regs, [HI64, LO64]>; -multiclass Atomic2Ops64<PatFrag Op, string Opstr> { - def #NAME# : Atomic2Ops<Op, Opstr, CPU64Regs, CPURegs>, +multiclass Atomic2Ops64<PatFrag Op> { + def #NAME# : Atomic2Ops<Op, CPU64Regs, CPURegs>, Requires<[NotN64, HasStdEnc]>; - def _P8 : Atomic2Ops<Op, Opstr, CPU64Regs, CPU64Regs>, + def _P8 : Atomic2Ops<Op, CPU64Regs, CPU64Regs>, Requires<[IsN64, HasStdEnc]> { let isCodeGenOnly = 1; } } -multiclass AtomicCmpSwap64<PatFrag Op, string Width> { - def #NAME# : AtomicCmpSwap<Op, Width, CPU64Regs, CPURegs>, +multiclass AtomicCmpSwap64<PatFrag Op> { + def #NAME# : AtomicCmpSwap<Op, CPU64Regs, CPURegs>, Requires<[NotN64, HasStdEnc]>; - def _P8 : AtomicCmpSwap<Op, Width, CPU64Regs, CPU64Regs>, + def _P8 : AtomicCmpSwap<Op, CPU64Regs, CPU64Regs>, Requires<[IsN64, HasStdEnc]> { let isCodeGenOnly = 1; } @@ -66,14 +66,14 @@ multiclass AtomicCmpSwap64<PatFrag Op, string Width> { } let usesCustomInserter = 1, Predicates = [HasStdEnc], DecoderNamespace = "Mips64" in { - defm ATOMIC_LOAD_ADD_I64 : Atomic2Ops64<atomic_load_add_64, "load_add_64">; - defm ATOMIC_LOAD_SUB_I64 : Atomic2Ops64<atomic_load_sub_64, "load_sub_64">; - defm ATOMIC_LOAD_AND_I64 : Atomic2Ops64<atomic_load_and_64, "load_and_64">; - defm ATOMIC_LOAD_OR_I64 : Atomic2Ops64<atomic_load_or_64, "load_or_64">; - defm ATOMIC_LOAD_XOR_I64 : Atomic2Ops64<atomic_load_xor_64, "load_xor_64">; - defm ATOMIC_LOAD_NAND_I64 : Atomic2Ops64<atomic_load_nand_64, "load_nand_64">; - defm ATOMIC_SWAP_I64 : Atomic2Ops64<atomic_swap_64, "swap_64">; - defm ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap64<atomic_cmp_swap_64, "64">; + defm ATOMIC_LOAD_ADD_I64 : Atomic2Ops64<atomic_load_add_64>; + defm ATOMIC_LOAD_SUB_I64 : Atomic2Ops64<atomic_load_sub_64>; + defm ATOMIC_LOAD_AND_I64 : Atomic2Ops64<atomic_load_and_64>; + defm ATOMIC_LOAD_OR_I64 : Atomic2Ops64<atomic_load_or_64>; + defm ATOMIC_LOAD_XOR_I64 : Atomic2Ops64<atomic_load_xor_64>; + defm ATOMIC_LOAD_NAND_I64 : Atomic2Ops64<atomic_load_nand_64>; + defm ATOMIC_SWAP_I64 : Atomic2Ops64<atomic_swap_64>; + defm ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap64<atomic_cmp_swap_64>; } //===----------------------------------------------------------------------===// diff --git a/lib/Target/Mips/MipsDSPInstrFormats.td b/lib/Target/Mips/MipsDSPInstrFormats.td index 8e01d06596..a72a763fde 100644 --- a/lib/Target/Mips/MipsDSPInstrFormats.td +++ b/lib/Target/Mips/MipsDSPInstrFormats.td @@ -24,8 +24,9 @@ class DSPInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> { let Predicates = [HasDSP]; } -class PseudoDSP<dag outs, dag ins, list<dag> pattern>: - MipsPseudo<outs, ins, "", pattern> { +class PseudoDSP<dag outs, dag ins, list<dag> pattern, + InstrItinClass itin = IIPseudo>: + MipsPseudo<outs, ins, pattern, itin> { let Predicates = [HasDSP]; } diff --git a/lib/Target/Mips/MipsDSPInstrInfo.td b/lib/Target/Mips/MipsDSPInstrInfo.td index e28a1389b4..9531b91487 100644 --- a/lib/Target/Mips/MipsDSPInstrInfo.td +++ b/lib/Target/Mips/MipsDSPInstrInfo.td @@ -486,7 +486,7 @@ class MULT_DESC_BASE<string instr_asm> { } class BPOSGE32_PSEUDO_DESC_BASE<SDPatternOperator OpNode, InstrItinClass itin> : - MipsPseudo<(outs CPURegs:$dst), (ins), "", [(set CPURegs:$dst, (OpNode))]> { + MipsPseudo<(outs CPURegs:$dst), (ins), [(set CPURegs:$dst, (OpNode))]> { list<Register> Uses = [DSPCtrl]; bit usesCustomInserter = 1; } diff --git a/lib/Target/Mips/MipsInstrFPU.td b/lib/Target/Mips/MipsInstrFPU.td index 3abc986ab3..ab6f8ab770 100644 --- a/lib/Target/Mips/MipsInstrFPU.td +++ b/lib/Target/Mips/MipsInstrFPU.td @@ -437,14 +437,13 @@ def FCMP_D64 : CEQS_FT<"d", FGR64, IIFcmp, MipsFPCmp>, CEQS_FM<17>, //===----------------------------------------------------------------------===// // Floating Point Pseudo-Instructions //===----------------------------------------------------------------------===// -def MOVCCRToCCR : PseudoSE<(outs CCR:$dst), (ins CCR:$src), - "# MOVCCRToCCR", []>; +def MOVCCRToCCR : PseudoSE<(outs CCR:$dst), (ins CCR:$src), []>; // This pseudo instr gets expanded into 2 mtc1 instrs after register // allocation. def BuildPairF64 : PseudoSE<(outs AFGR64:$dst), - (ins CPURegs:$lo, CPURegs:$hi), "", + (ins CPURegs:$lo, CPURegs:$hi), [(set AFGR64:$dst, (MipsBuildPairF64 CPURegs:$lo, CPURegs:$hi))]>; // This pseudo instr gets expanded into 2 mfc1 instrs after register @@ -452,7 +451,7 @@ def BuildPairF64 : // if n is 0, lower part of src is extracted. // if n is 1, higher part of src is extracted. def ExtractElementF64 : - PseudoSE<(outs CPURegs:$dst), (ins AFGR64:$src, i32imm:$n), "", + PseudoSE<(outs CPURegs:$dst), (ins AFGR64:$src, i32imm:$n), [(set CPURegs:$dst, (MipsExtractElementF64 AFGR64:$src, imm:$n))]>; //===----------------------------------------------------------------------===// diff --git a/lib/Target/Mips/MipsInstrFormats.td b/lib/Target/Mips/MipsInstrFormats.td index 988ed96cef..b2633df21b 100644 --- a/lib/Target/Mips/MipsInstrFormats.td +++ b/lib/Target/Mips/MipsInstrFormats.td @@ -80,15 +80,17 @@ class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern, } // Mips Pseudo Instructions Format -class MipsPseudo<dag outs, dag ins, string asmstr, list<dag> pattern>: - MipsInst<outs, ins, asmstr, pattern, IIPseudo, Pseudo> { +class MipsPseudo<dag outs, dag ins, list<dag> pattern, + InstrItinClass itin = IIPseudo> : + MipsInst<outs, ins, "", pattern, itin, Pseudo> { let isCodeGenOnly = 1; let isPseudo = 1; } // Mips32/64 Pseudo Instruction Format -class PseudoSE<dag outs, dag ins, string asmstr, list<dag> pattern>: - MipsPseudo<outs, ins, asmstr, pattern> { +class PseudoSE<dag outs, dag ins, list<dag> pattern, + InstrItinClass itin = IIPseudo>: + MipsPseudo<outs, ins, pattern, itin> { let Predicates = [HasStdEnc]; } diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index b1e63abb37..4f5560ac15 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -789,32 +789,27 @@ class InsBase<bits<6> _funct, string instr_asm, RegisterClass RC>: } // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). -class Atomic2Ops<PatFrag Op, string Opstr, RegisterClass DRC, - RegisterClass PRC> : +class Atomic2Ops<PatFrag Op, RegisterClass DRC, RegisterClass PRC> : PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr), - !strconcat("atomic_", Opstr, "\t$dst, $ptr, $incr"), [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>; -multiclass Atomic2Ops32<PatFrag Op, string Opstr> { - def #NAME# : Atomic2Ops<Op, Opstr, CPURegs, CPURegs>, - Requires<[NotN64, HasStdEnc]>; - def _P8 : Atomic2Ops<Op, Opstr, CPURegs, CPU64Regs>, - Requires<[IsN64, HasStdEnc]> { +multiclass Atomic2Ops32<PatFrag Op> { + def #NAME# : Atomic2Ops<Op, CPURegs, CPURegs>, Requires<[NotN64, HasStdEnc]>; + def _P8 : Atomic2Ops<Op, CPURegs, CPU64Regs>, + Requires<[IsN64, HasStdEnc]> { let DecoderNamespace = "Mips64"; } } // Atomic Compare & Swap. -class AtomicCmpSwap<PatFrag Op, string Width, RegisterClass DRC, - RegisterClass PRC> : +class AtomicCmpSwap<PatFrag Op, RegisterClass DRC, RegisterClass PRC> : PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap), - !strconcat("atomic_cmp_swap_", Width, "\t$dst, $ptr, $cmp, $swap"), [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>; -multiclass AtomicCmpSwap32<PatFrag Op, string Width> { - def #NAME# : AtomicCmpSwap<Op, Width, CPURegs, CPURegs>, - Requires<[NotN64, HasStdEnc]>; - def _P8 : AtomicCmpSwap<Op, Width, CPURegs, CPU64Regs>, +multiclass AtomicCmpSwap32<PatFrag Op> { + def #NAME# : AtomicCmpSwap<Op, CPURegs, CPURegs>, + Requires<[NotN64, HasStdEnc]>; + def _P8 : AtomicCmpSwap<Op, CPURegs, CPU64Regs>, Requires<[IsN64, HasStdEnc]> { let DecoderNamespace = "Mips64"; } @@ -839,44 +834,42 @@ class SCBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> : // Return RA. let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in -def RetRA : PseudoSE<(outs), (ins), "", [(MipsRet)]>; +def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>; let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt), - "!ADJCALLSTACKDOWN $amt", [(callseq_start timm:$amt)]>; def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), - "!ADJCALLSTACKUP $amt1", [(callseq_end timm:$amt1, timm:$amt2)]>; } let usesCustomInserter = 1 in { - defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8, "load_add_8">; - defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16, "load_add_16">; - defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32, "load_add_32">; - defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8, "load_sub_8">; - defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16, "load_sub_16">; - defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32, "load_sub_32">; - defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8, "load_and_8">; - defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16, "load_and_16">; - defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32, "load_and_32">; - defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8, "load_or_8">; - defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16, "load_or_16">; - defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32, "load_or_32">; - defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8, "load_xor_8">; - defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16, "load_xor_16">; - defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32, "load_xor_32">; - defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8, "load_nand_8">; - defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16, "load_nand_16">; - defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32, "load_nand_32">; - - defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8, "swap_8">; - defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16, "swap_16">; - defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32, "swap_32">; - - defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8, "8">; - defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16, "16">; - defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32, "32">; + defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8>; + defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16>; + defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32>; + defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8>; + defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16>; + defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32>; + defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8>; + defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16>; + defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32>; + defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8>; + defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16>; + defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32>; + defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8>; + defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16>; + defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32>; + defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8>; + defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16>; + defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32>; + + defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8>; + defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16>; + defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32>; + + defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8>; + defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16>; + defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32>; } //===----------------------------------------------------------------------===// |