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| author | NAKAMURA Takumi <geek4civic@gmail.com> | 2013-10-28 04:07:38 +0000 |
|---|---|---|
| committer | NAKAMURA Takumi <geek4civic@gmail.com> | 2013-10-28 04:07:38 +0000 |
| commit | 1fe9069d53f586963d61523f7c5a7d41d80a9d8b (patch) | |
| tree | e08c9a1283cd66558c7cbb04d760e7b1c196852f | |
| parent | f3ad5745681ece7af3027fd2f82fadb0247242e8 (diff) | |
| download | llvm-1fe9069d53f586963d61523f7c5a7d41d80a9d8b.tar.gz llvm-1fe9069d53f586963d61523f7c5a7d41d80a9d8b.tar.bz2 llvm-1fe9069d53f586963d61523f7c5a7d41d80a9d8b.tar.xz | |
Prune utf8 chars in comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193512 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/Mips/Mips16InstrInfo.td | 6 | ||||
| -rw-r--r-- | lib/Target/R600/R600ISelLowering.cpp | 4 |
2 files changed, 5 insertions, 5 deletions
diff --git a/lib/Target/Mips/Mips16InstrInfo.td b/lib/Target/Mips/Mips16InstrInfo.td index 3e0d40e417..725a3a76a6 100644 --- a/lib/Target/Mips/Mips16InstrInfo.td +++ b/lib/Target/Mips/Mips16InstrInfo.td @@ -1106,7 +1106,7 @@ def ShRxRyOffMemX16: // // Format: SLL rx, ry, sa MIPS16e // Purpose: Shift Word Left Logical (Extended) -// To execute a left-shift of a word by a fixed number of bits—0 to 31 bits. +// To execute a left-shift of a word by a fixed number of bits-0 to 31 bits. // def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIAlu>; @@ -1202,7 +1202,7 @@ def SravRxRy16: FRxRxRy16_ins<0b00111, "srav", IIAlu>; // Format: SRA rx, ry, sa MIPS16e // Purpose: Shift Word Right Arithmetic (Extended) // To execute an arithmetic right-shift of a word by a fixed -// number of bits—1 to 8 bits. +// number of bits-1 to 8 bits. // def SraX16: FEXT_SHIFT16_ins<0b11, "sra", IIAlu>; @@ -1220,7 +1220,7 @@ def SrlvRxRy16: FRxRxRy16_ins<0b00110, "srlv", IIAlu>; // Format: SRL rx, ry, sa MIPS16e // Purpose: Shift Word Right Logical (Extended) // To execute a logical right-shift of a word by a fixed -// number of bits—1 to 31 bits. +// number of bits-1 to 31 bits. // def SrlX16: FEXT_SHIFT16_ins<0b10, "srl", IIAlu>; diff --git a/lib/Target/R600/R600ISelLowering.cpp b/lib/Target/R600/R600ISelLowering.cpp index dfcfeed5e4..3d424c6503 100644 --- a/lib/Target/R600/R600ISelLowering.cpp +++ b/lib/Target/R600/R600ISelLowering.cpp @@ -1525,8 +1525,8 @@ SDValue R600TargetLowering::PerformDAGCombine(SDNode *N, break; } - // insert_vector_elt (build_vector elt0, …, eltN), NewEltIdx, idx - // => build_vector elt0, …, NewEltIdx, …, eltN + // insert_vector_elt (build_vector elt0, ... , eltN), NewEltIdx, idx + // => build_vector elt0, ... , NewEltIdx, ... , eltN case ISD::INSERT_VECTOR_ELT: { SDValue InVec = N->getOperand(0); SDValue InVal = N->getOperand(1); |