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| author | Evan Cheng <evan.cheng@apple.com> | 2008-07-22 20:42:56 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2008-07-22 20:42:56 +0000 |
| commit | 292578676524036842aecb2d932e3995dddd9c2a (patch) | |
| tree | 025e03d5684a82bb7c90ec40219244ff5fe7dfd0 | |
| parent | a3da83270505fea08f0a4650aa082fa608db54fd (diff) | |
| download | llvm-292578676524036842aecb2d932e3995dddd9c2a.tar.gz llvm-292578676524036842aecb2d932e3995dddd9c2a.tar.bz2 llvm-292578676524036842aecb2d932e3995dddd9c2a.tar.xz | |
Fix pr2566: incorrect assumption about bit_convert. It doesn't not have to output a vector value. Patch by Nicolas Capens!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53932 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 3 | ||||
| -rw-r--r-- | test/CodeGen/X86/2008-07-22-CombinerCrash.ll | 16 |
2 files changed, 18 insertions, 1 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 726108a997..19723ba1b6 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -4953,7 +4953,8 @@ SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { // look though conversions that change things like v4f32 to v2f64. if (V->getOpcode() == ISD::BIT_CONVERT) { SDOperand ConvInput = V->getOperand(0); - if (ConvInput.getValueType().getVectorNumElements() == NumElts) + if (ConvInput.getValueType().isVector() && + ConvInput.getValueType().getVectorNumElements() == NumElts) V = ConvInput.Val; } diff --git a/test/CodeGen/X86/2008-07-22-CombinerCrash.ll b/test/CodeGen/X86/2008-07-22-CombinerCrash.ll new file mode 100644 index 0000000000..a18564f4f9 --- /dev/null +++ b/test/CodeGen/X86/2008-07-22-CombinerCrash.ll @@ -0,0 +1,16 @@ +; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 +; PR2566 + +external global i16 ; <i16*>:0 [#uses=1] +external global <4 x i16> ; <<4 x i16>*>:1 [#uses=1] + +declare void @abort() + +define void @t() nounwind { + load i16* @0 ; <i16>:1 [#uses=1] + zext i16 %1 to i64 ; <i64>:2 [#uses=1] + bitcast i64 %2 to <4 x i16> ; <<4 x i16>>:3 [#uses=1] + shufflevector <4 x i16> %3, <4 x i16> undef, <4 x i32> zeroinitializer ; <<4 x i16>>:4 [#uses=1] + store <4 x i16> %4, <4 x i16>* @1 + ret void +} |