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author | Tim Northover <tnorthover@apple.com> | 2014-03-13 09:00:13 +0000 |
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committer | Tim Northover <tnorthover@apple.com> | 2014-03-13 09:00:13 +0000 |
commit | 2d9f3bf9f97aa768ffba70c906b89bae01c27330 (patch) | |
tree | 4848824c065a981093e1cfc407f65e719a443933 | |
parent | a2b15f5079534ed51b1f0bf9158a1b3a5f4ae688 (diff) | |
download | llvm-2d9f3bf9f97aa768ffba70c906b89bae01c27330.tar.gz llvm-2d9f3bf9f97aa768ffba70c906b89bae01c27330.tar.bz2 llvm-2d9f3bf9f97aa768ffba70c906b89bae01c27330.tar.xz |
AArch64: error when both positional & named operands are used.
Only one instruction pair needed changing: SMULH & UMULH. The previous
code worked, but MC was doing extra work treating Ra as a valid
operand (which then got completely overwritten in MCCodeEmitter).
No behaviour change, so no tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203772 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/AArch64/AArch64.td | 4 | ||||
-rw-r--r-- | lib/Target/AArch64/AArch64InstrFormats.td | 4 | ||||
-rw-r--r-- | lib/Target/AArch64/AArch64InstrInfo.td | 3 |
3 files changed, 7 insertions, 4 deletions
diff --git a/lib/Target/AArch64/AArch64.td b/lib/Target/AArch64/AArch64.td index d0f9bd4600..e49afd60c8 100644 --- a/lib/Target/AArch64/AArch64.td +++ b/lib/Target/AArch64/AArch64.td @@ -70,7 +70,9 @@ include "AArch64CallingConv.td" include "AArch64InstrInfo.td" -def AArch64InstrInfo : InstrInfo; +def AArch64InstrInfo : InstrInfo { + let noNamedPositionallyEncodedOperands = 1; +} //===----------------------------------------------------------------------===// // Declare the target which we are implementing diff --git a/lib/Target/AArch64/AArch64InstrFormats.td b/lib/Target/AArch64/AArch64InstrFormats.td index 34f917caab..4cc3813203 100644 --- a/lib/Target/AArch64/AArch64InstrFormats.td +++ b/lib/Target/AArch64/AArch64InstrFormats.td @@ -346,15 +346,13 @@ class A64I_dp3<bit sf, bits<6> opcode, dag outs, dag ins, string asmstr, list<dag> patterns, InstrItinClass itin> : A64InstRdnm<outs, ins, asmstr, patterns, itin> { - bits<5> Ra; - let Inst{31} = sf; let Inst{30-29} = opcode{5-4}; let Inst{28-24} = 0b11011; let Inst{23-21} = opcode{3-1}; // Inherits Rm in 20-16 let Inst{15} = opcode{0}; - let Inst{14-10} = Ra; + // {14-10} mostly Ra, but unspecified for SMULH/UMULH // Inherits Rn in 9-5 // Inherits Rd in 4-0 } diff --git a/lib/Target/AArch64/AArch64InstrInfo.td b/lib/Target/AArch64/AArch64InstrInfo.td index 4588eb73c5..3dc66a1f23 100644 --- a/lib/Target/AArch64/AArch64InstrInfo.td +++ b/lib/Target/AArch64/AArch64InstrInfo.td @@ -1881,6 +1881,9 @@ class A64I_dp3_4operand<bit sf, bits<6> opcode, RegisterClass AccReg, !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Ra"), [(set AccTy:$Rd, pattern)], NoItinerary>, Sched<[WriteMAC, ReadMAC, ReadMAC, ReadMAC]> { + bits<5> Ra; + let Inst{14-10} = Ra; + RegisterClass AccGPR = AccReg; RegisterClass SrcGPR = SrcReg; } |