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author | Andrew Trick <atrick@apple.com> | 2012-09-21 05:06:40 +0000 |
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committer | Andrew Trick <atrick@apple.com> | 2012-09-21 05:06:40 +0000 |
commit | 2f1d5d44c088d7f600fb63aef07f785a0f9c4c1f (patch) | |
tree | 50b911a374af7a945a85c8e61abc616892a1eebc | |
parent | fe87c302aa600fdac6d80349cde21e06337f8bfe (diff) | |
download | llvm-2f1d5d44c088d7f600fb63aef07f785a0f9c4c1f.tar.gz llvm-2f1d5d44c088d7f600fb63aef07f785a0f9c4c1f.tar.bz2 llvm-2f1d5d44c088d7f600fb63aef07f785a0f9c4c1f.tar.xz |
Cortex-A9 latency fixes (w/ -schedmodel only).
Quick review against the manual revealed a few obvious mistakes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164361 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/ARM/ARMScheduleA9.td | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/lib/Target/ARM/ARMScheduleA9.td b/lib/Target/ARM/ARMScheduleA9.td index 4159a9ac11..404634fee9 100644 --- a/lib/Target/ARM/ARMScheduleA9.td +++ b/lib/Target/ARM/ARMScheduleA9.td @@ -1938,13 +1938,13 @@ def A9WriteFMulS : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 5; } def A9WriteFMulD : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 6; } def A9WriteFMAS : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 8; } def A9WriteFMAD : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 9; } -def A9WriteFDivS : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 10; } -def A9WriteFDivD : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 20; } -def A9WriteFSqrtS : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 13; } -def A9WriteFSqrtD : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 28; } +def A9WriteFDivS : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 15; } +def A9WriteFDivD : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 25; } +def A9WriteFSqrtS : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 17; } +def A9WriteFSqrtD : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 32; } // NEON has an odd mix of latencies. Simply name the write types by latency. -def A9WriteV1 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 2; } +def A9WriteV1 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 1; } def A9WriteV2 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 2; } def A9WriteV3 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 3; } def A9WriteV4 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 4; } |