diff options
| author | Hal Finkel <hfinkel@anl.gov> | 2013-03-27 13:20:52 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2013-03-27 13:20:52 +0000 |
| commit | 32e12df253de7993f5a9bb89668d98ec0454f623 (patch) | |
| tree | 5b0da5bae87ae9924846a3e1dabb1f63347b0df1 | |
| parent | fe37e6279ebbb4ba1eede4bcb8dfe732f0bbcb38 (diff) | |
| download | llvm-32e12df253de7993f5a9bb89668d98ec0454f623.tar.gz llvm-32e12df253de7993f5a9bb89668d98ec0454f623.tar.bz2 llvm-32e12df253de7993f5a9bb89668d98ec0454f623.tar.xz | |
Print PPC ZERO as 0 (not r0) even on Darwin
It seems that the Darwin PPC assembler requires r0 to be written as 0 when it
means 0 (at least in lwarx/stwcx.). Fixes PR15605.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178142 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/PowerPC/PPCRegisterInfo.td | 4 | ||||
| -rw-r--r-- | test/CodeGen/PowerPC/atomic-1.ll | 6 |
2 files changed, 5 insertions, 5 deletions
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.td b/lib/Target/PowerPC/PPCRegisterInfo.td index aa5584ee3c..57a25f5143 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.td +++ b/lib/Target/PowerPC/PPCRegisterInfo.td @@ -87,8 +87,8 @@ foreach Index = 0-31 in { } // The reprsentation of r0 when treated as the constant 0. -def ZERO : GPR<0, "r0">; -def ZERO8 : GP8<ZERO, "r0">; +def ZERO : GPR<0, "0">; +def ZERO8 : GP8<ZERO, "0">; // Representations of the frame pointer used by ISD::FRAMEADDR. def FP : GPR<0 /* arbitrary */, "**FRAME POINTER**">; diff --git a/test/CodeGen/PowerPC/atomic-1.ll b/test/CodeGen/PowerPC/atomic-1.ll index cbfa4094fb..838db20ddd 100644 --- a/test/CodeGen/PowerPC/atomic-1.ll +++ b/test/CodeGen/PowerPC/atomic-1.ll @@ -1,10 +1,10 @@ -; RUN: llc < %s -march=ppc32 | FileCheck %s +; RUN: llc < %s -mtriple=powerpc-apple-darwin -march=ppc32 | FileCheck %s define i32 @exchange_and_add(i32* %mem, i32 %val) nounwind { ; CHECK: exchange_and_add: -; CHECK: lwarx +; CHECK: lwarx {{r[0-9]+}}, 0, {{r[0-9]+}} %tmp = atomicrmw add i32* %mem, i32 %val monotonic -; CHECK: stwcx. +; CHECK: stwcx. {{r[0-9]+}}, 0, {{r[0-9]+}} ret i32 %tmp } |