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| author | Raul E. Silvera <rsilvera@google.com> | 2014-03-18 17:49:12 +0000 |
|---|---|---|
| committer | Raul E. Silvera <rsilvera@google.com> | 2014-03-18 17:49:12 +0000 |
| commit | 370981ad17f6ce2e04a5493b12b670b0f1991d65 (patch) | |
| tree | 2e7e123bf55d3cfe717927fdea8bb152fff1dd80 | |
| parent | e1ea4faca159ff8e6fba39d00fee8ea5b4b5efe8 (diff) | |
| download | llvm-370981ad17f6ce2e04a5493b12b670b0f1991d65.tar.gz llvm-370981ad17f6ce2e04a5493b12b670b0f1991d65.tar.bz2 llvm-370981ad17f6ce2e04a5493b12b670b0f1991d65.tar.xz | |
Add support for scalarizing/splitting vector bswap.
Summary:
SLP Vectorization of intrinsics (r203707) has exposed cases where the
expansion of vector bswap is failing (PR19151).
Reviewers: hfinkel
CC: chandlerc
Differential Revision: http://llvm-reviews.chandlerc.com/D3104
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204163 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 2 | ||||
| -rw-r--r-- | test/CodeGen/Mips/bswap.ll | 19 |
2 files changed, 21 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index 4f57bc3201..940a9c9059 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -65,6 +65,7 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) { case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break; case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break; case ISD::ANY_EXTEND: + case ISD::BSWAP: case ISD::CTLZ: case ISD::CTPOP: case ISD::CTTZ: @@ -533,6 +534,7 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) { SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi); break; + case ISD::BSWAP: case ISD::CONVERT_RNDSAT: case ISD::CTLZ: case ISD::CTTZ: diff --git a/test/CodeGen/Mips/bswap.ll b/test/CodeGen/Mips/bswap.ll index 4824388da1..22b3db41a6 100644 --- a/test/CodeGen/Mips/bswap.ll +++ b/test/CodeGen/Mips/bswap.ll @@ -22,7 +22,26 @@ entry: ret i64 %or.7 } +define <4 x i32> @bswapv4i32(<4 x i32> %x) nounwind readnone { +entry: +; MIPS32-LABEL: bswapv4i32: +; MIPS32: wsbh $[[R0:[0-9]+]] +; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16 +; MIPS32: wsbh $[[R0:[0-9]+]] +; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16 +; MIPS32: wsbh $[[R0:[0-9]+]] +; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16 +; MIPS32: wsbh $[[R0:[0-9]+]] +; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16 +; mips16: .ent bswapv4i32 + %ret = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %x) + ret <4 x i32> %ret +} + + + declare i32 @llvm.bswap.i32(i32) nounwind readnone declare i64 @llvm.bswap.i64(i64) nounwind readnone +declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>) nounwind readnone |