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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-06-01 07:38:21 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-06-01 07:38:21 +0000 |
| commit | 3871a03035b576f750bae188cb8de79f8106c074 (patch) | |
| tree | a60c06502d4bf6caf2a6e5f7a41c9f5213cdb17a | |
| parent | 0d9056d7660a6fecfdd704395e7f629e4f65c11c (diff) | |
| download | llvm-3871a03035b576f750bae188cb8de79f8106c074.tar.gz llvm-3871a03035b576f750bae188cb8de79f8106c074.tar.bz2 llvm-3871a03035b576f750bae188cb8de79f8106c074.tar.xz | |
R600: Set all float vector expands in the same place
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209988 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/R600/AMDGPUISelLowering.cpp | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/lib/Target/R600/AMDGPUISelLowering.cpp b/lib/Target/R600/AMDGPUISelLowering.cpp index 6c443ea828..7b6df9ac40 100644 --- a/lib/Target/R600/AMDGPUISelLowering.cpp +++ b/lib/Target/R600/AMDGPUISelLowering.cpp @@ -204,9 +204,6 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) : setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); - setOperationAction(ISD::FNEG, MVT::v2f32, Expand); - setOperationAction(ISD::FNEG, MVT::v4f32, Expand); - setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); setOperationAction(ISD::MUL, MVT::i64, Expand); @@ -216,8 +213,6 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) : setOperationAction(ISD::UDIVREM, MVT::i32, Custom); setOperationAction(ISD::UDIVREM, MVT::i64, Custom); setOperationAction(ISD::UREM, MVT::i32, Expand); - setOperationAction(ISD::VSELECT, MVT::v2f32, Expand); - setOperationAction(ISD::VSELECT, MVT::v4f32, Expand); static const MVT::SimpleValueType IntTypes[] = { MVT::v2i32, MVT::v4i32 @@ -261,7 +256,9 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) : setOperationAction(ISD::FSQRT, VT, Expand); setOperationAction(ISD::FSIN, VT, Expand); setOperationAction(ISD::FSUB, VT, Expand); + setOperationAction(ISD::FNEG, VT, Expand); setOperationAction(ISD::SELECT, VT, Expand); + setOperationAction(ISD::VSELECT, VT, Expand); } setTargetDAGCombine(ISD::MUL); |