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author | Bradley Smith <bradley.smith@arm.com> | 2014-04-09 14:43:01 +0000 |
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committer | Bradley Smith <bradley.smith@arm.com> | 2014-04-09 14:43:01 +0000 |
commit | 436fe613fc88c22f0e25d816f2c2e15c16b0c479 (patch) | |
tree | 0ace8d4248dd435145e2697914fe7e828d7bfe80 | |
parent | dcb9231b8aee77c4b63dc6d5affb02cf9535a8ed (diff) | |
download | llvm-436fe613fc88c22f0e25d816f2c2e15c16b0c479.tar.gz llvm-436fe613fc88c22f0e25d816f2c2e15c16b0c479.tar.bz2 llvm-436fe613fc88c22f0e25d816f2c2e15c16b0c479.tar.xz |
[ARM64] Port over the PostEncoderMethod from AArch64 for exclusive loads and stores, so the unused register fields are set to all-ones canonically but are recognised with any value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205874 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/ARM64/ARM64InstrFormats.td | 21 | ||||
-rw-r--r-- | lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp | 15 | ||||
-rw-r--r-- | test/MC/Disassembler/ARM64/canonical-form.txt | 5 |
3 files changed, 37 insertions, 4 deletions
diff --git a/lib/Target/ARM64/ARM64InstrFormats.td b/lib/Target/ARM64/ARM64InstrFormats.td index f78f96fe9f..f6811ee668 100644 --- a/lib/Target/ARM64/ARM64InstrFormats.td +++ b/lib/Target/ARM64/ARM64InstrFormats.td @@ -2901,6 +2901,18 @@ class StorePairNoAlloc<bits<2> opc, bit V, RegisterClass regtype, // True exclusive operations write to and/or read from the system's exclusive // monitors, which as far as a compiler is concerned can be modelled as a // random shared memory address. Hence LoadExclusive mayStore. +// +// Since these instructions have the undefined register bits set to 1 in +// their canonical form, we need a post encoder method to set those bits +// to 1 when encoding these instructions. We do this using the +// fixLoadStoreExclusive function. This function has template parameters: +// +// fixLoadStoreExclusive<int hasRs, int hasRt2> +// +// hasRs indicates that the instruction uses the Rs field, so we won't set +// it to 1 (and the same for Rt2). We don't need template parameters for +// the other register fields since Rt and Rn are always used. +// let hasSideEffects = 1, mayLoad = 1, mayStore = 1 in class BaseLoadStoreExclusive<bits<2> sz, bit o2, bit L, bit o1, bit o0, dag oops, dag iops, string asm, string operands> @@ -2921,10 +2933,10 @@ class LoadStoreExclusiveSimple<bits<2> sz, bit o2, bit L, bit o1, bit o0, : BaseLoadStoreExclusive<sz, o2, L, o1, o0, oops, iops, asm, operands> { bits<5> reg; bits<5> base; - let Inst{20-16} = 0b11111; - let Inst{14-10} = 0b11111; let Inst{9-5} = base; let Inst{4-0} = reg; + + let PostEncoderMethod = "fixLoadStoreExclusive<0,0>"; } // Simple load acquires don't set the exclusive monitor @@ -2951,10 +2963,11 @@ class LoadExclusivePair<bits<2> sz, bit o2, bit L, bit o1, bit o0, bits<5> dst1; bits<5> dst2; bits<5> base; - let Inst{20-16} = 0b11111; let Inst{14-10} = dst2; let Inst{9-5} = base; let Inst{4-0} = dst1; + + let PostEncoderMethod = "fixLoadStoreExclusive<0,1>"; } // Simple store release operations do not check the exclusive monitor. @@ -2977,11 +2990,11 @@ class StoreExclusive<bits<2> sz, bit o2, bit L, bit o1, bit o0, bits<5> reg; bits<5> base; let Inst{20-16} = status; - let Inst{14-10} = 0b11111; let Inst{9-5} = base; let Inst{4-0} = reg; let Constraints = "@earlyclobber $Ws"; + let PostEncoderMethod = "fixLoadStoreExclusive<1,0>"; } class StoreExclusivePair<bits<2> sz, bit o2, bit L, bit o1, bit o0, diff --git a/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp b/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp index ce96d8e383..48172d894a 100644 --- a/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp +++ b/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp @@ -176,6 +176,11 @@ public: void EncodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const; + + template<int hasRs, int hasRt2> unsigned + fixLoadStoreExclusive(const MCInst &MI, unsigned EncodedValue, + const MCSubtargetInfo &STI) const; + }; } // end anonymous namespace @@ -560,4 +565,14 @@ void ARM64MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS, ++MCNumEmitted; // Keep track of the # of mi's emitted. } +template<int hasRs, int hasRt2> unsigned +ARM64MCCodeEmitter::fixLoadStoreExclusive(const MCInst &MI, + unsigned EncodedValue, + const MCSubtargetInfo &STI) const { + if (!hasRs) EncodedValue |= 0x001F0000; + if (!hasRt2) EncodedValue |= 0x00007C00; + + return EncodedValue; +} + #include "ARM64GenMCCodeEmitter.inc" diff --git a/test/MC/Disassembler/ARM64/canonical-form.txt b/test/MC/Disassembler/ARM64/canonical-form.txt new file mode 100644 index 0000000000..6aaa5da398 --- /dev/null +++ b/test/MC/Disassembler/ARM64/canonical-form.txt @@ -0,0 +1,5 @@ +# RUN: llvm-mc -triple arm64-apple-darwin --disassemble < %s | FileCheck %s + +0x00 0x08 0x00 0xc8 + +# CHECK: stxr w0, x0, [x0] |