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author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-05-08 18:01:56 +0000 |
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committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-05-08 18:01:56 +0000 |
commit | 459ff08eaadf1431bd3681e5607cb624fe9a4ffb (patch) | |
tree | 955e2af5efe1a219088fb854cf9bda7ec145312a | |
parent | 2413bf30046836a27a060a1ede4671d0c6e0759a (diff) | |
download | llvm-459ff08eaadf1431bd3681e5607cb624fe9a4ffb.tar.gz llvm-459ff08eaadf1431bd3681e5607cb624fe9a4ffb.tar.bz2 llvm-459ff08eaadf1431bd3681e5607cb624fe9a4ffb.tar.xz |
R600: Promote f64 vector load/stores to i64 for consistency
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208344 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/R600/AMDGPUISelLowering.cpp | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/lib/Target/R600/AMDGPUISelLowering.cpp b/lib/Target/R600/AMDGPUISelLowering.cpp index b34691a2a7..f4053802b9 100644 --- a/lib/Target/R600/AMDGPUISelLowering.cpp +++ b/lib/Target/R600/AMDGPUISelLowering.cpp @@ -130,6 +130,9 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) : setOperationAction(ISD::STORE, MVT::f64, Promote); AddPromotedToType(ISD::STORE, MVT::f64, MVT::i64); + setOperationAction(ISD::STORE, MVT::v2f64, Promote); + AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v2i64); + // Custom lowering of vector stores is required for local address space // stores. setOperationAction(ISD::STORE, MVT::v4i32, Custom); @@ -170,6 +173,9 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) : setOperationAction(ISD::LOAD, MVT::f64, Promote); AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64); + setOperationAction(ISD::LOAD, MVT::v2f64, Promote); + AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v2i64); + setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom); setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom); setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom); |