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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-08-16 01:12:00 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-08-16 01:12:00 +0000 |
| commit | 4781d314b7b0bd239dc3986b4157726e80a270ba (patch) | |
| tree | 14e00a8ea62034836af2f92ca88147267fbee245 | |
| parent | 6b88cdb34cc78f815946b8ebe6c2332d084526ad (diff) | |
| download | llvm-4781d314b7b0bd239dc3986b4157726e80a270ba.tar.gz llvm-4781d314b7b0bd239dc3986b4157726e80a270ba.tar.bz2 llvm-4781d314b7b0bd239dc3986b4157726e80a270ba.tar.xz | |
R600: Add support for v4i32 stores on Cayman
Tested-by: Aaron Watry <awatry@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188518 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/R600/R600Instructions.td | 1 | ||||
| -rw-r--r-- | test/CodeGen/R600/store.ll | 14 | ||||
| -rw-r--r-- | test/CodeGen/R600/vertex-fetch-encoding.ll | 2 |
3 files changed, 16 insertions, 1 deletions
diff --git a/lib/Target/R600/R600Instructions.td b/lib/Target/R600/R600Instructions.td index bacedfc0a6..06886ce056 100644 --- a/lib/Target/R600/R600Instructions.td +++ b/lib/Target/R600/R600Instructions.td @@ -1808,6 +1808,7 @@ class RAT_STORE_DWORD <RegisterClass rc, ValueType vt, bits<4> mask> : def RAT_STORE_DWORD32 : RAT_STORE_DWORD <R600_TReg32_X, i32, 0x1>; def RAT_STORE_DWORD64 : RAT_STORE_DWORD <R600_Reg64, v2i32, 0x3>; +def RAT_STORE_DWORD128 : RAT_STORE_DWORD <R600_Reg128, v4i32, 0xf>; class VTX_READ_cm <string name, bits<8> buffer_id, dag outs, list<dag> pattern> : VTX_WORD0_cm, VTX_READ<name, buffer_id, outs, pattern> { diff --git a/test/CodeGen/R600/store.ll b/test/CodeGen/R600/store.ll index 5dc0a84bbe..f2a8dd7d26 100644 --- a/test/CodeGen/R600/store.ll +++ b/test/CodeGen/R600/store.ll @@ -31,6 +31,20 @@ entry: ret void } +; EG-CHECK: @store_v4i32 +; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW +; EG-CHECK-NOT: MEM_RAT_CACHELESS STORE_RAW +; CM-CHECK: @store_v4i32 +; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD +; CM-CHECK-NOT: MEM_RAT_CACHELESS STORE_DWORD +; SI-CHECK: @store_v4i32 +; SI-CHECK: BUFFER_STORE_DWORDX4 +define void @store_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %in) { +entry: + store <4 x i32> %in, <4 x i32> addrspace(1)* %out + ret void +} + ; The stores in this function are combined by the optimizer to create a ; 64-bit store with 32-bit alignment. This is legal for SI and the legalizer ; should not try to split the 64-bit store back into 2 32-bit stores. diff --git a/test/CodeGen/R600/vertex-fetch-encoding.ll b/test/CodeGen/R600/vertex-fetch-encoding.ll index d892229f49..7ea7a5c079 100644 --- a/test/CodeGen/R600/vertex-fetch-encoding.ll +++ b/test/CodeGen/R600/vertex-fetch-encoding.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=barts | FileCheck --check-prefix=NI-CHECK %s -; RUN: not llc < %s -march=r600 -show-mc-encoding -mcpu=cayman | FileCheck --check-prefix=CM-CHECK %s +; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=cayman | FileCheck --check-prefix=CM-CHECK %s ; NI-CHECK: @vtx_fetch32 ; NI-CHECK: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0 ; encoding: [0x40,0x01,0x0[[GPR]],0x10,0x0[[GPR]],0xf0,0x5f,0x13,0x00,0x00,0x08,0x00 |