Remove OptimizeForSize global. Use function attribute optsize.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56937 91177308-0d34-0410-b5e6-96231b3b80d8

10 files changed, 26 insertions, 16 deletions

diff --git a/include/llvm/Target/TargetOptions.h b/include/llvm/Target/TargetOptions.h
index 42011d928c..b7b27a47ed 100644
--- a/include/llvm/Target/TargetOptions.h
+++ b/include/llvm/Target/TargetOptions.h
@@ -83,10 +83,6 @@ namespace llvm {
   /// optimization (pop the caller's stack) providing it supports it.
   extern bool PerformTailCallOpt;
 
-  /// OptimizeForSize - When this flag is set, the code generator avoids 
-  /// optimizations that increase size.
-  extern bool OptimizeForSize;
-
   /// StackAlignment - Override default stack alignment for target.
   extern unsigned StackAlignment;
 
diff --git a/lib/CodeGen/LLVMTargetMachine.cpp b/lib/CodeGen/LLVMTargetMachine.cpp
index bd8d499973..cd444552f7 100644
--- a/lib/CodeGen/LLVMTargetMachine.cpp
+++ b/lib/CodeGen/LLVMTargetMachine.cpp
@@ -81,7 +81,7 @@ LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
   if (addPreEmitPass(PM, Fast) && PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
 
-  if (!Fast && !OptimizeForSize)
+  if (!Fast)
     PM.add(createLoopAlignerPass());
 
   switch (FileType) {
diff --git a/lib/CodeGen/LoopAligner.cpp b/lib/CodeGen/LoopAligner.cpp
index 6cca8e5bad..60e3f19430 100644
--- a/lib/CodeGen/LoopAligner.cpp
+++ b/lib/CodeGen/LoopAligner.cpp
@@ -58,6 +58,10 @@ bool LoopAligner::runOnMachineFunction(MachineFunction &MF) {
   if (!Align)
     return false;  // Don't care about loop alignment.
 
+  const Function *F = MF.getFunction();
+  if (!F->isDeclaration() && F->hasFnAttr(Attribute::OptimizeForSize))
+    return false;
+
   for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
     MachineBasicBlock *MBB = I;
     if (MLI->isLoopHeader(MBB))
diff --git a/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp b/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
index 53ba8803c7..d8451bd1b8 100644
--- a/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
+++ b/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
@@ -776,7 +776,7 @@ bool PPCDarwinAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
 
   printVisibility(CurrentFnName, F->getVisibility());
 
-  EmitAlignment(OptimizeForSize ? 2 : 4, F);
+  EmitAlignment(F->hasFnAttr(Attribute::OptimizeForSize) ? 2 : 4, F);
   O << CurrentFnName << ":\n";
 
   // Emit pre-function debug information.
diff --git a/lib/Target/TargetMachine.cpp b/lib/Target/TargetMachine.cpp
index 600a120e86..90efb74bc9 100644
--- a/lib/Target/TargetMachine.cpp
+++ b/lib/Target/TargetMachine.cpp
@@ -35,7 +35,6 @@ namespace llvm {
   Reloc::Model RelocationModel;
   CodeModel::Model CMModel;
   bool PerformTailCallOpt;
-  bool OptimizeForSize;
   unsigned StackAlignment;
   bool RealignStack;
   bool VerboseAsm;
@@ -134,11 +133,6 @@ EnablePerformTailCallOpt("tailcallopt",
                          cl::desc("Turn on tail call optimization."),
                          cl::location(PerformTailCallOpt),
                          cl::init(false));
-static cl::opt<bool, true>
-EnableOptimizeForSize("optimize-size",
-                      cl::desc("Optimize for size."),
-                      cl::location(OptimizeForSize),
-                      cl::init(false));
 
 static cl::opt<unsigned, true>
 OverrideStackAlignment("stack-alignment",
diff --git a/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp b/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
index 366a5429a3..9415871442 100644
--- a/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
+++ b/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
@@ -153,7 +153,7 @@ void X86ATTAsmPrinter::emitFunctionHeader(const MachineFunction &MF) {
 
   SwitchToSection(TAI->SectionForGlobal(F));
 
-  unsigned FnAlign = OptimizeForSize ? 1 : 4;
+  unsigned FnAlign = 4;
   if (!F->isDeclaration() && F->hasFnAttr(Attribute::OptimizeForSize))
     FnAlign = 1;
   switch (F->getLinkage()) {
diff --git a/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp b/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
index c8199c59cf..fdec3bc713 100644
--- a/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
+++ b/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
@@ -140,7 +140,7 @@ bool X86IntelAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
 
   SwitchToTextSection("_text", F);
 
-  unsigned FnAlign = OptimizeForSize ? 1 : 4;
+  unsigned FnAlign = 4;
   if (!F->isDeclaration() && F->hasFnAttr(Attribute::OptimizeForSize))
     FnAlign = 1;
   switch (F->getLinkage()) {
diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp
index 2b7bf15d84..ea3dbad0ee 100644
--- a/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -137,7 +137,7 @@ namespace {
         ContainsFPCode(false), TM(tm),
         X86Lowering(*TM.getTargetLowering()),
         Subtarget(&TM.getSubtarget<X86Subtarget>()),
-        OptForSize(OptimizeForSize) {}
+        OptForSize(false) {}
 
     virtual const char *getPassName() const {
       return "X86 DAG->DAG Instruction Selection";
diff --git a/test/CodeGen/X86/vec_shuffle-23.ll b/test/CodeGen/X86/vec_shuffle-23.ll
index 34d84ef15f..7e8aa5dc4b 100644
--- a/test/CodeGen/X86/vec_shuffle-23.ll
+++ b/test/CodeGen/X86/vec_shuffle-23.ll
@@ -1,6 +1,5 @@
 ; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2                | not grep punpck
 ; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2                |     grep pshufd
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -optimize-size |     grep punpck
 
 define i32 @t() nounwind {
 entry:
diff --git a/test/CodeGen/X86/vec_shuffle-24.ll b/test/CodeGen/X86/vec_shuffle-24.ll
new file mode 100644
index 0000000000..170ba35173
--- /dev/null
+++ b/test/CodeGen/X86/vec_shuffle-24.ll
@@ -0,0 +1,17 @@
+; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2  |     grep punpck
+
+define i32 @t() nounwind optsize {
+entry:
+	%a = alloca <4 x i32>		; <<4 x i32>*> [#uses=2]
+	%b = alloca <4 x i32>		; <<4 x i32>*> [#uses=5]
+	volatile store <4 x i32> < i32 0, i32 1, i32 2, i32 3 >, <4 x i32>* %a
+	%tmp = load <4 x i32>* %a		; <<4 x i32>> [#uses=1]
+	store <4 x i32> %tmp, <4 x i32>* %b
+	%tmp1 = load <4 x i32>* %b		; <<4 x i32>> [#uses=1]
+	%tmp2 = load <4 x i32>* %b		; <<4 x i32>> [#uses=1]
+	%punpckldq = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> < i32 0, i32 4, i32 1, i32 5 >		; <<4 x i32>> [#uses=1]
+	store <4 x i32> %punpckldq, <4 x i32>* %b
+	%tmp3 = load <4 x i32>* %b		; <<4 x i32>> [#uses=1]
+	%result = extractelement <4 x i32> %tmp3, i32 0		; <i32> [#uses=1]
+	ret i32 %result
+}