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| author | Aaron Ballman <aaron@aaronballman.com> | 2014-05-19 14:29:04 +0000 |
|---|---|---|
| committer | Aaron Ballman <aaron@aaronballman.com> | 2014-05-19 14:29:04 +0000 |
| commit | 50d09f1212a8fc60426f8d419423bb3027c417e3 (patch) | |
| tree | 1a2fb7025dd31097ab49ab4dfe8ec0492cf1870e | |
| parent | 29e068bac01be735cfb6fcacf16bbe1819cf37bc (diff) | |
| download | llvm-50d09f1212a8fc60426f8d419423bb3027c417e3.tar.gz llvm-50d09f1212a8fc60426f8d419423bb3027c417e3.tar.bz2 llvm-50d09f1212a8fc60426f8d419423bb3027c417e3.tar.xz | |
Resolving MSVC warnings about switch statements with a default label, but no case labels. No functional changes intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209126 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM64/ARM64InstrInfo.cpp | 11 | ||||
| -rw-r--r-- | lib/Target/R600/AMDGPUMCInstLower.cpp | 6 |
2 files changed, 6 insertions, 11 deletions
diff --git a/lib/Target/ARM64/ARM64InstrInfo.cpp b/lib/Target/ARM64/ARM64InstrInfo.cpp index 75d906d9da..e4112655f8 100644 --- a/lib/Target/ARM64/ARM64InstrInfo.cpp +++ b/lib/Target/ARM64/ARM64InstrInfo.cpp @@ -827,14 +827,11 @@ bool ARM64InstrInfo::optimizeCompareInstr( /// Return true if this is this instruction has a non-zero immediate bool ARM64InstrInfo::hasNonZeroImm(const MachineInstr *MI) const { - switch (MI->getOpcode()) { - default: - if (MI->getOperand(3).isImm()) { - unsigned val = MI->getOperand(3).getImm(); - return (val != 0); - } - break; + if (MI->getOperand(3).isImm()) { + unsigned val = MI->getOperand(3).getImm(); + return (val != 0); } + return false; } diff --git a/lib/Target/R600/AMDGPUMCInstLower.cpp b/lib/Target/R600/AMDGPUMCInstLower.cpp index 66d1074321..b759495ad8 100644 --- a/lib/Target/R600/AMDGPUMCInstLower.cpp +++ b/lib/Target/R600/AMDGPUMCInstLower.cpp @@ -37,10 +37,8 @@ AMDGPUMCInstLower::AMDGPUMCInstLower(MCContext &ctx, const AMDGPUSubtarget &st): { } enum AMDGPUMCInstLower::SISubtarget -AMDGPUMCInstLower::AMDGPUSubtargetToSISubtarget(unsigned Gen) const { - switch (Gen) { - default: return AMDGPUMCInstLower::SI; - } +AMDGPUMCInstLower::AMDGPUSubtargetToSISubtarget(unsigned) const { + return AMDGPUMCInstLower::SI; } unsigned AMDGPUMCInstLower::getMCOpcode(unsigned MIOpcode) const { |