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authorEli Friedman <eli.friedman@gmail.com>2011-04-27 01:34:27 +0000
committerEli Friedman <eli.friedman@gmail.com>2011-04-27 01:34:27 +0000
commit547eb4fd560cdd77e06c88eed1722bdb94c82b26 (patch)
tree229fcef2bd3c86f640ebc98e23f9f12b879cffe5
parent3f95c88162cf319bce463d0e5e2d99a96c24dff6 (diff)
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Fix an edge case involving branches in fast-isel on x86.
rdar://problem/9303306 . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130272 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/X86/X86FastISel.cpp6
-rw-r--r--test/CodeGen/X86/fast-isel-i1.ll39
2 files changed, 34 insertions, 11 deletions
diff --git a/lib/Target/X86/X86FastISel.cpp b/lib/Target/X86/X86FastISel.cpp
index b35ec0d3a3..257b4741ce 100644
--- a/lib/Target/X86/X86FastISel.cpp
+++ b/lib/Target/X86/X86FastISel.cpp
@@ -1098,11 +1098,13 @@ bool X86FastISel::X86SelectBranch(const Instruction *I) {
}
// Otherwise do a clumsy setcc and re-test it.
+ // Note that i1 essentially gets ANY_EXTEND'ed to i8 where it isn't used
+ // in an explicit cast, so make sure to handle that correctly.
unsigned OpReg = getRegForValue(BI->getCondition());
if (OpReg == 0) return false;
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TEST8rr))
- .addReg(OpReg).addReg(OpReg);
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TEST8ri))
+ .addReg(OpReg).addImm(1);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::JNE_4))
.addMBB(TrueMBB);
FastEmitBranch(FalseMBB, DL);
diff --git a/test/CodeGen/X86/fast-isel-i1.ll b/test/CodeGen/X86/fast-isel-i1.ll
index d0665783ce..5d572c1de5 100644
--- a/test/CodeGen/X86/fast-isel-i1.ll
+++ b/test/CodeGen/X86/fast-isel-i1.ll
@@ -1,19 +1,40 @@
-; RUN: llc < %s -march=x86 -fast-isel | grep {andb \$1, %}
+; RUN: llc < %s -march=x86 -fast-isel | FileCheck %s
-declare i64 @bar(i64)
+declare i64 @test1a(i64)
-define i32 @foo(i64 %x) nounwind {
- %y = add i64 %x, -3 ; <i64> [#uses=1]
- %t = call i64 @bar(i64 %y) ; <i64> [#uses=1]
- %s = mul i64 %t, 77 ; <i64> [#uses=1]
- %z = trunc i64 %s to i1 ; <i1> [#uses=1]
+define i32 @test1(i64 %x) nounwind {
+; CHECK: test1:
+; CHECK: andb $1, %
+ %y = add i64 %x, -3
+ %t = call i64 @test1a(i64 %y)
+ %s = mul i64 %t, 77
+ %z = trunc i64 %s to i1
br label %next
next: ; preds = %0
- %u = zext i1 %z to i32 ; <i32> [#uses=1]
- %v = add i32 %u, 1999 ; <i32> [#uses=1]
+ %u = zext i1 %z to i32
+ %v = add i32 %u, 1999
br label %exit
exit: ; preds = %next
ret i32 %v
}
+
+define void @test2(i8* %a) nounwind {
+entry:
+; CHECK: test2:
+; CHECK: movb {{.*}} %al
+; CHECK-NEXT: xorb $1, %al
+; CHECK-NEXT: testb $1
+ %tmp = load i8* %a, align 1
+ %tobool = trunc i8 %tmp to i1
+ %tobool2 = xor i1 %tobool, true
+ br i1 %tobool2, label %if.then, label %if.end
+
+if.then:
+ call void @test2(i8* null)
+ br label %if.end
+
+if.end:
+ ret void
+}