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| author | Akira Hatanaka <ahatanaka@mips.com> | 2012-05-09 01:38:13 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-05-09 01:38:13 +0000 |
| commit | 56ec9f2c09afebc42ecf243eaaab598daa15957b (patch) | |
| tree | 641fa1373cb71c1c0a7824fa504b88b596d592b8 | |
| parent | a284acb8a79468f378452826b2426b4bcdc27e94 (diff) | |
| download | llvm-56ec9f2c09afebc42ecf243eaaab598daa15957b.tar.gz llvm-56ec9f2c09afebc42ecf243eaaab598daa15957b.tar.bz2 llvm-56ec9f2c09afebc42ecf243eaaab598daa15957b.tar.xz | |
Make register FP allocatable if the compiled function does not have dynamic
allocas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156458 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/Mips/MipsRegisterInfo.cpp | 10 | ||||
| -rw-r--r-- | test/CodeGen/Mips/fp-spill-reload.ll | 39 |
2 files changed, 47 insertions, 2 deletions
diff --git a/lib/Target/Mips/MipsRegisterInfo.cpp b/lib/Target/Mips/MipsRegisterInfo.cpp index 952666301a..aa632235d2 100644 --- a/lib/Target/Mips/MipsRegisterInfo.cpp +++ b/lib/Target/Mips/MipsRegisterInfo.cpp @@ -85,12 +85,12 @@ BitVector MipsRegisterInfo:: getReservedRegs(const MachineFunction &MF) const { static const uint16_t ReservedCPURegs[] = { Mips::ZERO, Mips::AT, Mips::K0, Mips::K1, - Mips::SP, Mips::FP, Mips::RA + Mips::SP, Mips::RA }; static const uint16_t ReservedCPU64Regs[] = { Mips::ZERO_64, Mips::AT_64, Mips::K0_64, Mips::K1_64, - Mips::SP_64, Mips::FP_64, Mips::RA_64 + Mips::SP_64, Mips::RA_64 }; BitVector Reserved(getNumRegs()); @@ -124,6 +124,12 @@ getReservedRegs(const MachineFunction &MF) const { Reserved.set(Mips::GP_64); } + // If this function has dynamic allocas, reserve FP. + if (MF.getTarget().getFrameLowering()->hasFP(MF)) { + Reserved.set(Mips::FP); + Reserved.set(Mips::FP_64); + } + // Reserve hardware registers. Reserved.set(Mips::HWR29); Reserved.set(Mips::HWR29_64); diff --git a/test/CodeGen/Mips/fp-spill-reload.ll b/test/CodeGen/Mips/fp-spill-reload.ll new file mode 100644 index 0000000000..f9887a5582 --- /dev/null +++ b/test/CodeGen/Mips/fp-spill-reload.ll @@ -0,0 +1,39 @@ +; RUN: llc -march=mipsel < %s | FileCheck %s +; check that $fp is not reserved. + +define void @foo0(i32* nocapture %b) nounwind { +entry: +; CHECK: sw $fp +; CHECK: lw $fp + %0 = load i32* %b, align 4 + %arrayidx.1 = getelementptr inbounds i32* %b, i32 1 + %1 = load i32* %arrayidx.1, align 4 + %add.1 = add nsw i32 %1, 1 + %arrayidx.2 = getelementptr inbounds i32* %b, i32 2 + %2 = load i32* %arrayidx.2, align 4 + %add.2 = add nsw i32 %2, 2 + %arrayidx.3 = getelementptr inbounds i32* %b, i32 3 + %3 = load i32* %arrayidx.3, align 4 + %add.3 = add nsw i32 %3, 3 + %arrayidx.4 = getelementptr inbounds i32* %b, i32 4 + %4 = load i32* %arrayidx.4, align 4 + %add.4 = add nsw i32 %4, 4 + %arrayidx.5 = getelementptr inbounds i32* %b, i32 5 + %5 = load i32* %arrayidx.5, align 4 + %add.5 = add nsw i32 %5, 5 + %arrayidx.6 = getelementptr inbounds i32* %b, i32 6 + %6 = load i32* %arrayidx.6, align 4 + %add.6 = add nsw i32 %6, 6 + %arrayidx.7 = getelementptr inbounds i32* %b, i32 7 + %7 = load i32* %arrayidx.7, align 4 + %add.7 = add nsw i32 %7, 7 + call void @foo2(i32 %0, i32 %add.1, i32 %add.2, i32 %add.3, i32 %add.4, i32 %add.5, i32 %add.6, i32 %add.7) nounwind + call void bitcast (void (...)* @foo1 to void ()*)() nounwind + call void @foo2(i32 %0, i32 %add.1, i32 %add.2, i32 %add.3, i32 %add.4, i32 %add.5, i32 %add.6, i32 %add.7) nounwind + ret void +} + +declare void @foo2(i32, i32, i32, i32, i32, i32, i32, i32) + +declare void @foo1(...) + |