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| author | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2011-07-29 02:05:28 +0000 |
|---|---|---|
| committer | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2011-07-29 02:05:28 +0000 |
| commit | 6126005259422581d165e406af0e46de19c0b401 (patch) | |
| tree | 7e629b281adec130bef984d18a5b508390ff2832 | |
| parent | dd6353073f8345e76716e5785da5a48bc964eac9 (diff) | |
| download | llvm-6126005259422581d165e406af0e46de19c0b401.tar.gz llvm-6126005259422581d165e406af0e46de19c0b401.tar.bz2 llvm-6126005259422581d165e406af0e46de19c0b401.tar.xz | |
Fix two tests that I crashed in the previous commits. The mask elts
on the second half must be reindexed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136454 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 22 | ||||
| -rw-r--r-- | test/CodeGen/X86/avx-vpermil.ll | 2 |
2 files changed, 18 insertions, 6 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index e35d9e9813..5987e57a69 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -3159,7 +3159,13 @@ static bool isCommutedSHUFP(ShuffleVectorSDNode *N) { /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand /// specifies a shuffle of elements that is suitable for input to MOVHLPS. bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) { - if (N->getValueType(0).getVectorNumElements() != 4) + EVT VT = N->getValueType(0); + unsigned NumElems = VT.getVectorNumElements(); + + if (VT.getSizeInBits() != 128) + return false; + + if (NumElems != 4) return false; // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 @@ -3173,15 +3179,19 @@ bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) { /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, /// <2, 3, 2, 3> bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) { - unsigned NumElems = N->getValueType(0).getVectorNumElements(); + EVT VT = N->getValueType(0); + unsigned NumElems = VT.getVectorNumElements(); + + if (VT.getSizeInBits() != 128) + return false; if (NumElems != 4) return false; return isUndefOrEqual(N->getMaskElt(0), 2) && - isUndefOrEqual(N->getMaskElt(1), 3) && - isUndefOrEqual(N->getMaskElt(2), 2) && - isUndefOrEqual(N->getMaskElt(3), 3); + isUndefOrEqual(N->getMaskElt(1), 3) && + isUndefOrEqual(N->getMaskElt(2), 2) && + isUndefOrEqual(N->getMaskElt(3), 3); } /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand @@ -3501,6 +3511,8 @@ static unsigned getShuffleVPERMILPSImmediate(SDNode *N) { int MaskElt = SVOp->getMaskElt(i+(l*LaneSize)); if (MaskElt < 0) continue; + if (MaskElt >= LaneSize) + MaskElt -= LaneSize; Mask |= MaskElt << (i*2); } } diff --git a/test/CodeGen/X86/avx-vpermil.ll b/test/CodeGen/X86/avx-vpermil.ll index a3e916dc1e..f83a4450cf 100644 --- a/test/CodeGen/X86/avx-vpermil.ll +++ b/test/CodeGen/X86/avx-vpermil.ll @@ -31,7 +31,7 @@ entry: ; vpermil should match masks like this: <u,3,1,2,4,u,5,6>. Check that the ; target specific mask was correctly generated. ; CHECK: vpermilps $-100 -define <8 x float> @funcA(<8 x float> %a) nounwind uwtable readnone ssp { +define <8 x float> @funcE(<8 x float> %a) nounwind uwtable readnone ssp { entry: %shuffle = shufflevector <8 x float> %a, <8 x float> undef, <8 x i32> <i32 8, i32 3, i32 1, i32 2, i32 4, i32 8, i32 5, i32 6> ret <8 x float> %shuffle |