diff options
| author | Hal Finkel <hfinkel@anl.gov> | 2013-07-08 06:16:58 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2013-07-08 06:16:58 +0000 |
| commit | 63e7a38c8980d70197ecdb9ba54b79b87c7b064d (patch) | |
| tree | 6b7cb7f93339b3eb90387b74f3688b672c553481 | |
| parent | 5310cdbcc909a7c35d4c7df0fd5703850a9db2a5 (diff) | |
| download | llvm-63e7a38c8980d70197ecdb9ba54b79b87c7b064d.tar.gz llvm-63e7a38c8980d70197ecdb9ba54b79b87c7b064d.tar.bz2 llvm-63e7a38c8980d70197ecdb9ba54b79b87c7b064d.tar.xz | |
Fix PromoteIntRes_BUILD_VECTOR crash with i1 vectors
This fixes a bug (found by llvm-stress) in
DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR where it assumed that the result
type would always be larger than the original operands. This is not always
true, however, with boolean vectors. For example, promoting a node of type v8i1
(where the operands will be of type i32, the type to which i1 is promoted) will
yield a node with a result vector element type of i16 (and operands of type
i32). As a result, we cannot blindly assume that we can ANY_EXTEND the operands
to the result type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185794 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp | 8 | ||||
| -rw-r--r-- | test/CodeGen/PowerPC/bv-pres-v8i1.ll | 39 |
2 files changed, 46 insertions, 1 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp index b3ec9bc022..df388981ae 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp @@ -2930,7 +2930,13 @@ SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(SDNode *N) { SmallVector<SDValue, 8> Ops; Ops.reserve(NumElems); for (unsigned i = 0; i != NumElems; ++i) { - SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(i)); + SDValue Op; + // It is possible for the operands to be larger than the result, for example, + // when the operands are promoted booleans and the result was an i1 vector. + if (N->getOperand(i).getValueType().bitsLT(NOutVTElem)) + Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(i)); + else + Op = N->getOperand(i); Ops.push_back(Op); } diff --git a/test/CodeGen/PowerPC/bv-pres-v8i1.ll b/test/CodeGen/PowerPC/bv-pres-v8i1.ll new file mode 100644 index 0000000000..5bf84ed1c5 --- /dev/null +++ b/test/CodeGen/PowerPC/bv-pres-v8i1.ll @@ -0,0 +1,39 @@ +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s +target triple = "powerpc64-unknown-linux-gnu" + +define void @autogen_SD70() { +BB: + br label %CF78 + +CF78: ; preds = %CF87, %CF78, %BB + br i1 undef, label %CF78, label %CF87 + +CF87: ; preds = %CF78 + %Cmp19 = icmp sge <8 x i1> zeroinitializer, zeroinitializer + %Cmp26 = icmp slt i32 -1, undef + br i1 %Cmp26, label %CF78, label %CF79 + +CF79: ; preds = %CF79, %CF87 + br i1 undef, label %CF79, label %CF82 + +CF82: ; preds = %CF82, %CF79 + br i1 undef, label %CF82, label %CF84 + +CF84: ; preds = %CF82 + br label %CF + +CF: ; preds = %CF88, %CF, %CF84 + br i1 undef, label %CF, label %CF85 + +CF85: ; preds = %CF85, %CF + %I52 = insertelement <8 x i1> %Cmp19, i1 %Cmp26, i32 6 + %Cmp61 = icmp ult i32 477567, undef + br i1 %Cmp61, label %CF85, label %CF88 + +CF88: ; preds = %CF85 + %E63 = extractelement <8 x i1> %I52, i32 5 + br i1 %E63, label %CF, label %CF80 + +CF80: ; preds = %CF80, %CF88 + br label %CF80 +} |